Use gcc -Wimplicit-fallthrough=2 by default if available

GCC 7 instroduced -Wimplicit-fallthrough
https://developers.redhat.com/blog/2017/03/10/wimplicit-fallthrough-in-gcc-7/

It caught a couple of bugs, but it does need a bit of extra comments to
explain when a switch case statement fall-through is deliberate. Luckily
with -Wimplicit-fallthrough=2 various existing comments already do that.
I have fixed the bugs, but adding explicit break statements where
necessary and added comments where the fall-through was correct.

https://bugs.kde.org/show_bug.cgi?id=405430

diff --git a/Makefile.all.am b/Makefile.all.am
index daa7e413f8f0b2eb43a2a6326510e8377a23bca5..3786e34933174d725eb602b664866429beabe8ad 100644 (file)
--- a/Makefile.all.am
+++ b/Makefile.all.am
@@ -115,6 +115,7 @@ AM_CFLAGS_BASE = \
        @FLAG_W_MISSING_PARAMETER_TYPE@ \
        @FLAG_W_LOGICAL_OP@ \
        @FLAG_W_ENUM_CONVERSION@ \
+       @FLAG_W_IMPLICIT_FALLTHROUGH@ \
        @FLAG_W_OLD_STYLE_DECLARATION@ \
        @FLAG_FINLINE_FUNCTIONS@ \
        @FLAG_FNO_STACK_PROTECTOR@ \

diff --git a/NEWS b/NEWS
index bf90093c59ea107365d89253ac0acbfb6dcd654c..0b432a13c37dce7e9b001ddfcc25a6e2d21555ab 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -119,6 +119,7 @@ where XXXXXX is the bug number as listed below.
 405363  PPC64, xvcvdpsxws, xvcvdpuxws, do not handle NaN arguments correctly.
 405365  PPC64, function _get_maxmin_fp_NaN() doesn't handle QNaN, SNaN case
         correctly.
+405430  Use gcc -Wimplicit-fallthrough=2 by default if available
 405733  PPC64, xvcvdpsp should write 32-bit result to upper and lower 32-bits
         of the 64-bit destination field.
 405734  PPC64, vrlwnm, vrlwmi, vrldrm, vrldmi do not work properly when me < mb

diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c
index 7e57933d51994eee384c9d1c13fc1520a816e619..7a20d45238b888c8dc22b695e147d889a9f1a7f7 100644 (file)
--- a/VEX/priv/guest_amd64_toIR.c
+++ b/VEX/priv/guest_amd64_toIR.c
@@ -30914,6 +30914,7 @@ Long dis_ESC_0F3A__VEX (
 #        undef CVT
          goto decode_success;
       }
+      break;
 
    case 0x09:
       /* VROUNDPD imm8, xmm2/m128, xmm1 */
@@ -31007,6 +31008,7 @@ Long dis_ESC_0F3A__VEX (
 #        undef CVT
          goto decode_success;
       }
+      break;
 
    case 0x0A:
    case 0x0B:

diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
index 476eedc9edcf16d01043b77e97b5e2165fc6cff4..64c6982c9d3cfe8d44dcf549ae25c7683189498f 100644 (file)
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -6419,8 +6419,8 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn,
                } else {
                   storeLE(addr, getQRegLane((tt+3) % 32, ix, ty));
                }
-               /* fallthrough */
             }
+            /* fallthrough */
             case 3: {
                IRExpr* addr
                   = binop(Iop_Add64, mkexpr(tTA), mkU64(2 * laneSzB));
@@ -6429,8 +6429,8 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn,
                } else {
                   storeLE(addr, getQRegLane((tt+2) % 32, ix, ty));
                }
-               /* fallthrough */
             }
+            /* fallthrough */
             case 2: {
                IRExpr* addr
                   = binop(Iop_Add64, mkexpr(tTA), mkU64(1 * laneSzB));
@@ -6439,8 +6439,8 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn,
                } else {
                   storeLE(addr, getQRegLane((tt+1) % 32, ix, ty));
                }
-               /* fallthrough */
             }
+            /* fallthrough */
             case 1: {
                IRExpr* addr
                   = binop(Iop_Add64, mkexpr(tTA), mkU64(0 * laneSzB));

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index 35a62a18c058bbf2b344182c3d4374b69b78fa8d..5b63a809ae27ec97b51f451acb75c4fad4d03ade 100644 (file)
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -6507,9 +6507,8 @@ Bool dis_neon_data_2reg_and_shift ( UInt theInstr, IRTemp condT )
                }
                return True;
             }
-         } else {
-            /* fall through */
          }
+         /* else fall through */
       case 9:
          dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF);
          mreg = ((theInstr >>  1) & 0x10) | (theInstr & 0xF);

diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c
index d05816e28c4aaaaf9127f23e06558db743dd7282..4748ba4f30ca419dc65fbd4225d788fef701c8ef 100644 (file)
--- a/VEX/priv/guest_mips_toIR.c
+++ b/VEX/priv/guest_mips_toIR.c
@@ -26348,7 +26348,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
             /* Conditions starting with S should signal exception on QNaN inputs. */
             switch (function) {
                case 8:  /* SAF */
-                  signaling = CMPSAFD;
+                  signaling = CMPSAFD; /* fallthrough */
                case 0: /* AF */
                   assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft)));
                   calculateFCSR(fs, ft, signaling, False, 2);
@@ -26357,7 +26357,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                 get_IR_roundingmode(), mkU64(0)));
                   break;
                case 9: /* SUN */
-                  signaling = CMPSAFD;
+                  signaling = CMPSAFD; /* fallthrough */
                case 1: /* UN */
                   assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft)));
                   calculateFCSR(fs, ft, signaling, False, 2);
@@ -26369,7 +26369,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                            get_IR_roundingmode(), mkU64(0))));
                   break;
                case 0x19: /* SOR */
-                  signaling = CMPSAFD;
+                  signaling = CMPSAFD; /* fallthrough */
                case 0x11: /* OR */
                   assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft)));
                   calculateFCSR(fs, ft, signaling, False, 2);
@@ -26381,7 +26381,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                           mkU64(0xFFFFFFFFFFFFFFFFULL))));
                   break;
                case 0xa: /* SEQ */
-                  signaling = CMPSAFD;
+                  signaling = CMPSAFD; /* fallthrough */
                case 2: /* EQ */
                   assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft)));
                   calculateFCSR(fs, ft, signaling, False, 2);
@@ -26393,7 +26393,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                            get_IR_roundingmode(), mkU64(0))));
                   break;
                case 0x1A: /* SNEQ */
-                  signaling = CMPSAFD;
+                  signaling = CMPSAFD; /* fallthrough */
                case 0x12: /* NEQ */
                   assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft)));
                   calculateFCSR(fs, ft, signaling, False, 2);
@@ -26405,7 +26405,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                           mkU64(0xFFFFFFFFFFFFFFFFULL))));
                   break;
                case 0xB: /* SUEQ */
-                  signaling = CMPSAFD;
+                  signaling = CMPSAFD; /* fallthrough */
                case 0x3: /* UEQ */
                   assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft)));
                   calculateFCSR(fs, ft, signaling, False, 2);
@@ -26422,7 +26422,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                                       mkU64(0)))));
                   break;
                case 0x1B:  /* SNEQ */
-                  signaling = CMPSAFD;
+                  signaling = CMPSAFD; /* fallthrough */
                case 0x13:  /* NEQ */
                   assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft)));
                   calculateFCSR(fs, ft, signaling, False, 2);
@@ -26439,7 +26439,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                                       mkU64(0)))));
                   break;
                case 0xC: /* SLT */
-                  signaling = CMPSAFD;
+                  signaling = CMPSAFD; /* fallthrough */
                case 0x4: /* LT */
                   assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft)));
                   calculateFCSR(fs, ft, signaling, False, 2);
@@ -26451,7 +26451,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                            get_IR_roundingmode(), mkU64(0))));
                   break;
                case 0xD: /* SULT */
-                  signaling = CMPSAFD;
+                  signaling = CMPSAFD; /* fallthrough */
                case 0x5: /* ULT */
                   assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft)));
                   calculateFCSR(fs, ft, signaling, False, 2);
@@ -26468,7 +26468,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                                      mkU64(0)))));
                   break;
                case 0xE: /* SLE */
-                  signaling = CMPSAFD;
+                  signaling = CMPSAFD; /* fallthrough */
                case 0x6: /* LE */
                   assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft)));
                   calculateFCSR(fs, ft, signaling, False, 2);
@@ -26485,7 +26485,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                                       mkU64(0)))));
                   break;
                case 0xF: /* SULE */
-                  signaling = CMPSAFD;
+                  signaling = CMPSAFD; /* fallthrough */
                case 0x7: /* ULE */
                   assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft)));
                   calculateFCSR(fs, ft, signaling, False, 2);
@@ -26514,7 +26514,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
             /* Conditions starting with S should signal exception on QNaN inputs. */
             switch (function) {
                case 8:  /* SAF */
-                  signaling = CMPSAFS;
+                  signaling = CMPSAFS; /* fallthrough */
                case 0: /* AF */
                   assign(t0, binop(Iop_CmpF32,
                                    getLoFromF64(Ity_F64, getFReg(fs)),
@@ -26526,7 +26526,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                                get_IR_roundingmode(), mkU32(0))));
                   break;
                case 9: /* SUN */
-                  signaling = CMPSAFS;
+                  signaling = CMPSAFS; /* fallthrough */
                case 1: /* UN */
                   assign(t0, binop(Iop_CmpF32,
                                    getLoFromF64(Ity_F64, getFReg(fs)),
@@ -26543,7 +26543,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                                           mkU32(0)))));
                   break;
                case 0x19: /* SOR */
-                  signaling = CMPSAFS;
+                  signaling = CMPSAFS; /* fallthrough */
                case 0x11: /* OR */
                   assign(t0, binop(Iop_CmpF32,
                                    getLoFromF64(Ity_F64, getFReg(fs)),
@@ -26560,7 +26560,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                                     mkU32(0xFFFFFFFFU)))));
                   break;
                case 0xa: /* SEQ */
-                  signaling = CMPSAFS;
+                  signaling = CMPSAFS; /* fallthrough */
                case 2: /* EQ */
                   assign(t0, binop(Iop_CmpF32,
                                    getLoFromF64(Ity_F64, getFReg(fs)),
@@ -26577,7 +26577,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                                           mkU32(0)))));
                   break;
                case 0x1A: /* SNEQ */
-                  signaling = CMPSAFS;
+                  signaling = CMPSAFS; /* fallthrough */
                case 0x12: /* NEQ */
                   assign(t0, binop(Iop_CmpF32,
                                    getLoFromF64(Ity_F64, getFReg(fs)),
@@ -26594,7 +26594,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                                          mkU32(0xFFFFFFFFU)))));
                   break;
                case 0xB: /* SUEQ */
-                  signaling = CMPSAFS;
+                  signaling = CMPSAFS; /* fallthrough */
                case 0x3: /* UEQ */
                   assign(t0, binop(Iop_CmpF32,
                                    getLoFromF64(Ity_F64, getFReg(fs)),
@@ -26616,7 +26616,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                                                      mkU32(0))))));
                   break;
                case 0x1B:  /* SNEQ */
-                  signaling = CMPSAFS;
+                  signaling = CMPSAFS; /* fallthrough */
                case 0x13:  /* NEQ */
                   assign(t0, binop(Iop_CmpF32,
                                    getLoFromF64(Ity_F64, getFReg(fs)),
@@ -26638,7 +26638,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                                                      mkU32(0))))));
                   break;
                case 0xC: /* SLT */
-                  signaling = CMPSAFS;
+                  signaling = CMPSAFS; /* fallthrough */
                case 0x4: /* LT */
                   assign(t0, binop(Iop_CmpF32,
                                    getLoFromF64(Ity_F64, getFReg(fs)),
@@ -26655,7 +26655,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                                           mkU32(0)))));
                   break;
                case 0xD: /* SULT */
-                  signaling = CMPSAFS;
+                  signaling = CMPSAFS; /* fallthrough */
                case 0x5: /* ULT */
                   assign(t0, binop(Iop_CmpF32,
                                    getLoFromF64(Ity_F64, getFReg(fs)),
@@ -26677,7 +26677,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                                                      mkU32(0))))));
                   break;
                case 0xE: /* SLE */
-                  signaling = CMPSAFS;
+                  signaling = CMPSAFS; /* fallthrough */
                case 0x6: /* LE */
                   assign(t0, binop(Iop_CmpF32,
                                    getLoFromF64(Ity_F64, getFReg(fs)),
@@ -26699,7 +26699,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                                                                      mkU32(0))))));
                   break;
                case 0xF: /* SULE */
-                  signaling = CMPSAFS;
+                  signaling = CMPSAFS; /* fallthrough */
                case 0x7: /* ULE */
                   assign(t0, binop(Iop_CmpF32,
                                    getLoFromF64(Ity_F64, getFReg(fs)),
@@ -28051,6 +28051,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
                         break;
                      } else {
                         ILLEGAL_INSTRUCTON;
+                        break;
                      }
 
                   }
@@ -31583,6 +31584,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
             }
          } else {
             ILLEGAL_INSTRUCTON;
+            break;
          }
 
       }

diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index ab14cf87eadb6888c89d17f2694f9a948fdf0784..ec7c63a6fc2a611cbcca3a4e7b77a9452f7d6253 100644 (file)
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -7429,6 +7429,7 @@ static Bool dis_int_store ( UInt theInstr, const VexAbiInfo* vbi )
    case 0x3E: // immediate offset: 64bit: std/stdu/stq: mask off
               // lowest 2 bits of immediate before forming EA
       simm16 = simm16 & 0xFFFFFFFC;
+      /* fallthrough */
    default:   // immediate offset
       assign( EA, ea_rAor0_simm( rA_addr, simm16  ) );
       break;
@@ -28424,6 +28425,7 @@ DisResult disInstr_PPC_WRK (
             if (!allow_DFP) goto decode_noDFP;
             if (dis_dfp_arith( theInstr ))
                goto decode_success;
+            goto decode_failure;
          case 0x82:   // dcmpo, DFP comparison ordered instruction
          case 0x282:  // dcmpu, DFP comparison unordered instruction
             if (!allow_DFP) goto decode_noDFP;
@@ -28904,6 +28906,7 @@ DisResult disInstr_PPC_WRK (
                                                                  abiinfo ) )
                goto decode_success;
          }
+         /* fallthrough to dis_vx_scalar_quad_precision */
 
          /* Instructions implemented with Pre ISA 3.0 Iops */
          /* VSX Scalar Quad-Precision instructions */

diff --git a/VEX/priv/guest_x86_toIR.c b/VEX/priv/guest_x86_toIR.c
index 2e3b80303e2d141e18d70f471fd113c869e9be11..9a6e417d63e678ac086ed71c04c5946f4d383f85 100644 (file)
--- a/VEX/priv/guest_x86_toIR.c
+++ b/VEX/priv/guest_x86_toIR.c
@@ -14295,25 +14295,25 @@ DisResult disInstr_X86_WRK (
       switch (abyte) {
       /* According to the Intel manual, "repne movs" should never occur, but
        * in practice it has happened, so allow for it here... */
-      case 0xA4: sz = 1;   /* REPNE MOVS<sz> */
+      case 0xA4: sz = 1;   /* REPNE MOVS<sz> fallthrough */
       case 0xA5: 
          dis_REP_op ( &dres, X86CondNZ, dis_MOVS, sz, eip_orig,
                              guest_EIP_bbstart+delta, "repne movs" );
          break;
 
-      case 0xA6: sz = 1;   /* REPNE CMP<sz> */
+      case 0xA6: sz = 1;   /* REPNE CMP<sz> fallthrough */
       case 0xA7:
          dis_REP_op ( &dres, X86CondNZ, dis_CMPS, sz, eip_orig, 
                              guest_EIP_bbstart+delta, "repne cmps" );
          break;
 
-      case 0xAA: sz = 1;   /* REPNE STOS<sz> */
+      case 0xAA: sz = 1;   /* REPNE STOS<sz> fallthrough */
       case 0xAB:
          dis_REP_op ( &dres, X86CondNZ, dis_STOS, sz, eip_orig, 
                              guest_EIP_bbstart+delta, "repne stos" );
          break;
 
-      case 0xAE: sz = 1;   /* REPNE SCAS<sz> */
+      case 0xAE: sz = 1;   /* REPNE SCAS<sz> fallthrough */
       case 0xAF:
          dis_REP_op ( &dres, X86CondNZ, dis_SCAS, sz, eip_orig,
                              guest_EIP_bbstart+delta, "repne scas" );
@@ -14351,31 +14351,31 @@ DisResult disInstr_X86_WRK (
          }
          break;
 
-      case 0xA4: sz = 1;   /* REP MOVS<sz> */
+      case 0xA4: sz = 1;   /* REP MOVS<sz> fallthrough */
       case 0xA5:
          dis_REP_op ( &dres, X86CondAlways, dis_MOVS, sz, eip_orig, 
                              guest_EIP_bbstart+delta, "rep movs" );
          break;
 
-      case 0xA6: sz = 1;   /* REPE CMP<sz> */
+      case 0xA6: sz = 1;   /* REPE CMP<sz> fallthrough */
       case 0xA7:
          dis_REP_op ( &dres, X86CondZ, dis_CMPS, sz, eip_orig, 
                              guest_EIP_bbstart+delta, "repe cmps" );
          break;
 
-      case 0xAA: sz = 1;   /* REP STOS<sz> */
+      case 0xAA: sz = 1;   /* REP STOS<sz> fallthrough */
       case 0xAB:
          dis_REP_op ( &dres, X86CondAlways, dis_STOS, sz, eip_orig, 
                              guest_EIP_bbstart+delta, "rep stos" );
          break;
 
-      case 0xAC: sz = 1;   /* REP LODS<sz> */
+      case 0xAC: sz = 1;   /* REP LODS<sz> fallthrough */
       case 0xAD:
          dis_REP_op ( &dres, X86CondAlways, dis_LODS, sz, eip_orig, 
                              guest_EIP_bbstart+delta, "rep lods" );
          break;
 
-      case 0xAE: sz = 1;   /* REPE SCAS<sz> */
+      case 0xAE: sz = 1;   /* REPE SCAS<sz> fallthrough */
       case 0xAF: 
          dis_REP_op ( &dres, X86CondZ, dis_SCAS, sz, eip_orig, 
                              guest_EIP_bbstart+delta, "repe scas" );

diff --git a/VEX/priv/host_arm64_isel.c b/VEX/priv/host_arm64_isel.c
index 50f9205d1d5d22c9ff949c9a05f90eeb64362c8b..49d0f0b19f00975de1dda8f66e02ea312cd22982 100644 (file)
--- a/VEX/priv/host_arm64_isel.c
+++ b/VEX/priv/host_arm64_isel.c
@@ -2040,7 +2040,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
          addInstr(env, ARM64Instr_MovI(dst, hregARM64_X0()));
          return dst;
       }
-      /* else fall through; will hit the irreducible: label */
+      goto irreducible;
    }
 
    /* --------- LITERAL --------- */

diff --git a/VEX/priv/host_arm_isel.c b/VEX/priv/host_arm_isel.c
index da4f4aa8094c4c88612bf106ea742138f174fd40..9ef4269660416bd174cdf00f9fe6bc0bda7a0a52 100644 (file)
--- a/VEX/priv/host_arm_isel.c
+++ b/VEX/priv/host_arm_isel.c
@@ -2001,7 +2001,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
          addInstr(env, mk_iMOVds_RR(dst, hregARM_R0()));
          return dst;
       }
-      /* else fall through; will hit the irreducible: label */
+      goto irreducible;
    }
 
    /* --------- LITERAL --------- */

diff --git a/VEX/priv/host_mips_defs.c b/VEX/priv/host_mips_defs.c
index 7a3faed48936c6622ad39af86eea972e8bde6c2f..717fd271ac693d9c6c85564a566029c1a35693c6 100644 (file)
--- a/VEX/priv/host_mips_defs.c
+++ b/VEX/priv/host_mips_defs.c
@@ -3396,10 +3396,10 @@ static UChar *mkFormBIT(UChar *p, UInt op, UInt df, UInt ms, UInt ws, UInt wd) {
    switch (df) {
       case 0:
          dfm |= 0x10;
-
+         /* fallthrough */
       case 1:
          dfm |= 0x20;
-
+         /* fallthrough */
       case 2:
          dfm |= 0x40;
    }

diff --git a/VEX/priv/host_mips_isel.c b/VEX/priv/host_mips_isel.c
index f6d5b0abeeb3ee10d1bcb340b298d899abf6c45b..c0cdfb084a5bd0144d5aa2a4263cc57b661af5f7 100644 (file)
--- a/VEX/priv/host_mips_isel.c
+++ b/VEX/priv/host_mips_isel.c
@@ -2022,18 +2022,21 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e)
             switch (op_unop) {
                case Iop_1Uto64:
                   vassert(mode64);
+                  /* fallthrough */
                case Iop_1Uto8:
                case Iop_1Uto32:
                   mask = toUShort(0x1);
                   break;
                case Iop_8Uto64:
                   vassert(mode64);
+                  /* fallthrough */
                case Iop_8Uto16:
                case Iop_8Uto32:
                   mask = toUShort(0xFF);
                   break;
                case Iop_16Uto64:
                   vassert(mode64);
+                  /* fallthrough */
                case Iop_16Uto32:
                   mask = toUShort(0xFFFF);
                   break;
@@ -2155,6 +2158,7 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e)
 
          case Iop_Clz64:
             vassert(mode64);
+           /* fallthrough */
          case Iop_Clz32: {
             HReg r_dst = newVRegI(env);
             HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);

diff --git a/configure.ac b/configure.ac
index 3c92f715232b15b471e28bc09f8c5829dee664a2..e26b5037c71868f0e3c3b2291fb6ce9e3c427932 100755 (executable)
--- a/configure.ac
+++ b/configure.ac
@@ -2113,6 +2113,7 @@ AC_GCC_WARNING_SUBST([ignored-qualifiers], [FLAG_W_IGNORED_QUALIFIERS])
 AC_GCC_WARNING_SUBST([missing-parameter-type], [FLAG_W_MISSING_PARAMETER_TYPE])
 AC_GCC_WARNING_SUBST([logical-op], [FLAG_W_LOGICAL_OP])
 AC_GCC_WARNING_SUBST([enum-conversion], [FLAG_W_ENUM_CONVERSION])
+AC_GCC_WARNING_SUBST([implicit-fallthrough=2], [FLAG_W_IMPLICIT_FALLTHROUGH])
 
 # Does this compiler support -Wformat-security ?
 # Special handling is needed, because certain GCC versions require -Wformat

diff --git a/coregrind/m_gdbserver/m_gdbserver.c b/coregrind/m_gdbserver/m_gdbserver.c
index 1f98ac9cc8927637c1a935082e977de4b56172bb..96372fd2642773b289bc66405e37e02b969f2e1a 100644 (file)
--- a/coregrind/m_gdbserver/m_gdbserver.c
+++ b/coregrind/m_gdbserver/m_gdbserver.c
@@ -911,7 +911,8 @@ void VG_(invoke_gdbserver) ( int check )
          interrupts_non_interruptible++;
          VG_(force_vgdb_poll) ();
          give_control_back_to_vgdb();
-
+         /* If give_control_back_to_vgdb returns in an non interruptable
+           state something went horribly wrong, fallthrough to vg_assert. */
       default:             vg_assert(0);
       }
    }

diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c
index 2f6ca3ddcf33c61f4c4396ab0f48946c50ce6810..73ef98d447c83a343ce5a53bf70c071b0e7b10ac 100644 (file)
--- a/coregrind/m_syswrap/syswrap-linux.c
+++ b/coregrind/m_syswrap/syswrap-linux.c
@@ -898,8 +898,8 @@ PRE(sys_clone)
       break;
 
    case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */
-      // FALLTHROUGH - assume vfork (somewhat) == fork, see ML_(do_fork_clone).
       cloneflags &= ~VKI_CLONE_VM;
+      // FALLTHROUGH - assume vfork (somewhat) == fork, see ML_(do_fork_clone).
 
    case 0: /* plain fork */
       SET_STATUS_from_SysRes(
@@ -11960,6 +11960,7 @@ PRE(sys_bpf)
                PRE_MEM_WRITE("bpf(attr->btf_log_buf)",
                              attr->btf_log_buf, attr->btf_log_size);
          }
+         break;
       case VKI_BPF_TASK_FD_QUERY:
          /* Get info about the task. Write collected info. */
          PRE_MEM_READ("bpf(attr->task_fd_query.pid)", (Addr)&attr->task_fd_query.pid, sizeof(attr->task_fd_query.pid));

diff --git a/memcheck/mc_malloc_wrappers.c b/memcheck/mc_malloc_wrappers.c
index 875eba758381ee3db2e269e94f22e36b1bad376c..caf097f62ea2ac30c510b31a7e2d0820d183d5fa 100644 (file)
--- a/memcheck/mc_malloc_wrappers.c
+++ b/memcheck/mc_malloc_wrappers.c
@@ -199,8 +199,8 @@ MC_Chunk* create_MC_Chunk ( ThreadId tid, Addr p, SizeT szB,
    mc->szB       = szB;
    mc->allockind = kind;
    switch ( MC_(n_where_pointers)() ) {
-      case 2: mc->where[1] = 0; // fallback to 1
-      case 1: mc->where[0] = 0; // fallback to 0
+      case 2: mc->where[1] = 0; // fallthrough to 1
+      case 1: mc->where[0] = 0; // fallthrough to 0
       case 0: break;
       default: tl_assert(0);
    }