arm64: dts: renesas: r9a09g077: Add ICU support

The Renesas RZ/T2H (R9A09G077) SoC has an Interrupt Controller (ICU)
block that routes external interrupts to the GIC's SPIs, with the
ability of level-translation, and can also produce software and
aggregate error interrupts.

Add support for it.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251201112933.488801-4-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index b0080392f75e27326d8753856451dd6ba4274723..63de8271f47c0133cf38190f5e4b20888f735e89 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -828,6 +828,79 @@
                        #power-domain-cells = <0>;
                };
 
+               icu: interrupt-controller@802a0000 {
+                       compatible = "renesas,r9a09g077-icu";
+                       reg = <0 0x802a0000 0 0x10000>,
+                             <0 0x812a0000 0 0x10000>;
+                       #interrupt-cells = <2>;
+                       #address-cells = <0>;
+                       interrupt-controller;
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 7 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 14 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 16 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 408 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 409 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 412 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 415 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 418 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "intcpu0", "intcpu1", "intcpu2",
+                                         "intcpu3", "intcpu4", "intcpu5",
+                                         "intcpu6", "intcpu7", "intcpu8",
+                                         "intcpu9", "intcpu10", "intcpu11",
+                                         "intcpu12", "intcpu13", "intcpu14",
+                                         "intcpu15",
+                                         "irq0", "irq1", "irq2", "irq3",
+                                         "irq4", "irq5", "irq6", "irq7",
+                                         "irq8", "irq9", "irq10", "irq11",
+                                         "irq12", "irq13", "irq14", "irq15",
+                                         "sei",
+                                         "ca55-err0", "ca55-err1",
+                                         "cr520-err0", "cr520-err1",
+                                         "cr521-err0", "cr521-err1",
+                                         "peri-err0", "peri-err1",
+                                         "dsmif-err0", "dsmif-err1",
+                                         "encif-err0", "encif-err1";
+                       clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+                       power-domains = <&cpg>;
+               };
+
                pinctrl: pinctrl@802c0000 {
                        compatible = "renesas,r9a09g077-pinctrl";
                        reg = <0 0x802c0000 0 0x10000>,