gcc-7-branch to support built-in functions.
gcc/ChangeLog:
2019-04-02 Xiong Hu Luo <luoxhu@linux.ibm.com>
Backport from trunk r250477.
2017-07-24 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c.c: Add support for built-in functions
vector float vec_extract_fp32_from_shorth (vector unsigned short);
vector float vec_extract_fp32_from_shortl (vector unsigned short);
* config/rs6000/altivec.h (vec_extract_fp_from_shorth,
vec_extract_fp_from_shortl): Add defines for the two builtins.
* config/rs6000/rs6000-builtin.def (VEXTRACT_FP_FROM_SHORTH,
VEXTRACT_FP_FROM_SHORTL): Add BU_P9V_OVERLOAD_1 and BU_P9V_VSX_1
new builtins.
* config/rs6000/vsx.md vsx_xvcvhpsp): Add define_insn.
(vextract_fp_from_shorth, vextract_fp_from_shortl): Add define_expands.
* doc/extend.texi: Update the built-in documentation file for the
new built-in function.
Backport from trunk r255555.
2017-12-11 Carl Love <cel@us.ibm.com>
* config/rs6000/altivec.h (vec_extract_fp32_from_shorth,
vec_extract_fp32_from_shortl]): Add #defines.
* config/rs6000/rs6000-builtin.def (VSLDOI_2DI): Add macro expansion.
* config/rs6000/rs6000-c.c (ALTIVEC_BUILTIN_VEC_UNPACKH,
ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VEC_AND,
ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VEC_SRL,
ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VEC_SLD,
ALTIVEC_BUILTIN_VEC_SLL): Add expansions.
* doc/extend.texi: Add documentation for the added builtins.
gcc/testsuite/ChangeLog:
2019-04-02 Xiong Hu Luo <luoxhu@linux.ibm.com>
Backport from trunk r250477.
2017-07-24 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-3-p9-runnable.c: Add new test file for
the new built-ins.
Backport from trunk r255555.
2017-12-11 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/altivec-7.c: Renamed altivec-7.h.
* gcc.target/powerpc/altivec-7.h (main): Add testcases for vec_unpackl.
Add dg-final tests for the instructions generated.
* gcc.target/powerpc/altivec-7-be.c: New file to test on big endian.
* gcc.target/powerpc/altivec-7-le.c: New file to test on little endian.
* gcc.target/powerpc/altivec-13.c (foo): Add vec_sld, vec_srl,
vec_sro testcases. Add dg-final tests for the instructions generated.
* gcc.target/powerpc/builtins-3-p8.c (test_vsi_packs_vui,
test_vsi_packs_vsi, test_vsi_packs_vssi, test_vsi_packs_vusi,
test_vsi_packsu-vssi, test_vsi_packsu-vusi, test_vsi_packsu-vsll,
test_vsi_packsu-vull, test_vsi_packsu-vsi, test_vsi_packsu-vui): Add
testcases. Add dg-final tests for new instructions.
* gcc.target/powerpc/p8vector-builtin-2.c (vbschar_eq, vbchar_eq,
vuchar_eq, vbint_eq, vsint_eq, viint_eq, vuint_eq, vbool_eq, vbint_ne,
vsint_ne, vuint_ne, vbool_ne, vsign_ne, vuns_ne, vbshort_ne): Add
tests.
Add dg-final instruction tests.
* gcc.target/powerpc/vsx-vector-6.c: Renamed vsx-vector-6.h.
* gcc.target/powerpc/vsx-vector-6.h (vec_andc,vec_nmsub, vec_nmadd,
vec_or, vec_nor, vec_andc, vec_or, vec_andc, vec_msums): Add tests.
Add dg-final tests for the generated instructions.
* gcc.target/powerpc/builtins-3.c (test_sll_vsc_vsc_vsuc,
test_sll_vuc_vuc, test_sll_vsi_vsi_vuc, test_sll_vui_vui_vuc,
test_sll_vbll_vull, test_sll_vbll_vbll_vus, test_sll_vp_vp_vuc,
test_sll_vssi_vssi_vuc, test_sll_vusi_vusi_vuc, test_slo_vsc_vsc_vsc,
test_slo_vuc_vuc_vsc, test_slo_vsi_vsi_vsc, test_slo_vsi_vsi_vuc,
test_slo_vui_vui_vsc, test_slo_vui_vui_vuc, test_slo_vsll_slo_vsll_vsc,
test_slo_vsll_slo_vsll_vuc, test_slo_vull_slo_vull_vsc,
test_slo_vull_slo_vull_vuc, test_slo_vp_vp_vsc, test_slo_vp_vp_vuc,
test_slo_vssi_vssi_vsc, test_slo_vssi_vssi_vuc, test_slo_vusi_vusi_vsc,
test_slo_vusi_vusi_vuc, test_slo_vusi_vusi_vuc, test_slo_vf_vf_vsc,
test_slo_vf_vf_vuc, test_cmpb_float): Add tests.
Backport from trunk r257253.
2018-01-31 Will Schmidt <will_schmidt@vnet.ibm.com>
* gcc.target/powerpc/altivec-13.c: Remove VSX-requiring built-ins.
* gcc.target/powerpc/vsx-13.c: New.
Backport from trunk r258137.
2018-03-02 Will Schmidt <will_schmidt@vnet.ibm.com>
* gcc.target/powerpc/altivec-7-be.c: Remove VSX content, allow
32-bit target.
* gcc.target/powerpc/altivec-7.h: Remove VSX content.
* gcc.target/powerpc/vsx-7-be.c: New test (VSX content).
* gcc.target/powerpc/vsx-7.h: New include (VSX content).
* gcc.target/powerpc/altivec-7-le.c: Add vsx-7.h include.
From-SVN: r270073
+2019-04-02 Xiong Hu Luo <luoxhu@linux.ibm.com>
+
+ Backport from trunk r250477.
+
+ 2017-07-24 Carl Love <cel@us.ibm.com>
+
+ * config/rs6000/rs6000-c.c: Add support for built-in functions
+ vector float vec_extract_fp32_from_shorth (vector unsigned short);
+ vector float vec_extract_fp32_from_shortl (vector unsigned short);
+ * config/rs6000/altivec.h (vec_extract_fp_from_shorth,
+ vec_extract_fp_from_shortl): Add defines for the two builtins.
+ * config/rs6000/rs6000-builtin.def (VEXTRACT_FP_FROM_SHORTH,
+ VEXTRACT_FP_FROM_SHORTL): Add BU_P9V_OVERLOAD_1 and BU_P9V_VSX_1
+ new builtins.
+ * config/rs6000/vsx.md vsx_xvcvhpsp): Add define_insn.
+ (vextract_fp_from_shorth, vextract_fp_from_shortl): Add define_expands.
+ * doc/extend.texi: Update the built-in documentation file for the
+ new built-in function.
+
+ Backport from trunk r255555.
+
+ 2017-12-11 Carl Love <cel@us.ibm.com>
+
+ * config/rs6000/altivec.h (vec_extract_fp32_from_shorth,
+ vec_extract_fp32_from_shortl]): Add #defines.
+ * config/rs6000/rs6000-builtin.def (VSLDOI_2DI): Add macro expansion.
+ * config/rs6000/rs6000-c.c (ALTIVEC_BUILTIN_VEC_UNPACKH,
+ ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VEC_AND,
+ ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VEC_SRL,
+ ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VEC_SLD,
+ ALTIVEC_BUILTIN_VEC_SLL): Add expansions.
+ * doc/extend.texi: Add documentation for the added builtins.
+
2019-03-28 Martin Liska <mliska@suse.cz>
Backport from mainline
#define vec_insert_exp __builtin_vec_insert_exp
#define vec_test_data_class __builtin_vec_test_data_class
+#define vec_extract_fp_from_shorth __builtin_vec_vextract_fp_from_shorth
+#define vec_extract_fp_from_shortl __builtin_vec_vextract_fp_from_shortl
+#define vec_extract_fp32_from_shorth __builtin_vec_vextract_fp_from_shorth
+#define vec_extract_fp32_from_shortl __builtin_vec_vextract_fp_from_shortl
+
#define scalar_extract_exp __builtin_vec_scalar_extract_exp
#define scalar_extract_sig __builtin_vec_scalar_extract_sig
#define scalar_insert_exp __builtin_vec_scalar_insert_exp
BU_ALTIVEC_3 (VSLDOI_16QI, "vsldoi_16qi", CONST, altivec_vsldoi_v16qi)
BU_ALTIVEC_3 (VSLDOI_8HI, "vsldoi_8hi", CONST, altivec_vsldoi_v8hi)
BU_ALTIVEC_3 (VSLDOI_4SI, "vsldoi_4si", CONST, altivec_vsldoi_v4si)
+BU_ALTIVEC_3 (VSLDOI_2DI, "vsldoi_2di", CONST, altivec_vsldoi_v2di)
BU_ALTIVEC_3 (VSLDOI_4SF, "vsldoi_4sf", CONST, altivec_vsldoi_v4sf)
BU_ALTIVEC_3 (VSLDOI_2DF, "vsldoi_2df", CONST, altivec_vsldoi_v2df)
BU_P9V_OVERLOAD_1 (REVB, "revb")
+BU_P9V_OVERLOAD_1 (VEXTRACT_FP_FROM_SHORTH, "vextract_fp_from_shorth")
+BU_P9V_OVERLOAD_1 (VEXTRACT_FP_FROM_SHORTL, "vextract_fp_from_shortl")
+
/* ISA 3.0 vector scalar overloaded 2 argument functions. */
BU_P9V_OVERLOAD_2 (VSIEDP, "scalar_insert_exp")
BU_P9V_VSX_1 (VEESP, "extract_exp_sp", CONST, xvxexpsp)
BU_P9V_VSX_1 (VESDP, "extract_sig_dp", CONST, xvxsigdp)
BU_P9V_VSX_1 (VESSP, "extract_sig_sp", CONST, xvxsigsp)
+BU_P9V_VSX_1 (VEXTRACT_FP_FROM_SHORTH, "vextract_fp_from_shorth", CONST, vextract_fp_from_shorth)
+BU_P9V_VSX_1 (VEXTRACT_FP_FROM_SHORTL, "vextract_fp_from_shortl", CONST, vextract_fp_from_shortl)
/* 2 argument vsx vector functions added in ISA 3.0 (power9). */
BU_P9V_VSX_2 (VIEDP, "insert_exp_dp", CONST, xviexpdp)
RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
+ { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
+ RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
+ { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
+ RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
{ ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
{ ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
+ { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
{ ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
{ ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
{ ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
+
+ { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
+ { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
+ { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
+ { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
+ { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V8HI, 0 },
+
{ ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
{ ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
{ ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
+ { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
+ { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
{ ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
{ ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
{ ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
+ { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
+ { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
+ { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
+ { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
+
{ ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
{ ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE },
{ ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
+ { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_NOT_OPAQUE },
+ { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
+ RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE },
+ { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI,
+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_NOT_OPAQUE },
+
{ ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
{ ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
{ P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
+ { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH,
+ RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
+ { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL,
+ RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
+
{ P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
RS6000_BTI_V16QI, 0 },
UNSPEC_VSX_CVDPSXWS
UNSPEC_VSX_CVDPUXWS
UNSPEC_VSX_CVSPDP
+ UNSPEC_VSX_CVHPSP
UNSPEC_VSX_CVSPDPN
UNSPEC_VSX_CVDPSPN
UNSPEC_VSX_CVSXWDP
UNSPEC_VSX_ROUND_I
UNSPEC_VSX_ROUND_IC
UNSPEC_VSX_SLDWI
+ UNSPEC_VSX_XXPERM
+
UNSPEC_VSX_XXSPLTW
UNSPEC_VSX_XXSPLTD
UNSPEC_VSX_DIVSD
UNSPEC_VSX_SIEXPDP
UNSPEC_VSX_SCMPEXPDP
UNSPEC_VSX_STSTDC
+ UNSPEC_VSX_VEXTRACT_FP_FROM_SHORTH
+ UNSPEC_VSX_VEXTRACT_FP_FROM_SHORTL
UNSPEC_VSX_VXEXP
UNSPEC_VSX_VXSIG
UNSPEC_VSX_VIEXP
"xscvspdp %x0,%x1"
[(set_attr "type" "fp")])
+;; Generate xvcvhpsp instruction
+(define_insn "vsx_xvcvhpsp"
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
+ (unspec:V4SF [(match_operand: V16QI 1 "vsx_register_operand" "wa")]
+ UNSPEC_VSX_CVHPSP))]
+ "TARGET_P9_VECTOR"
+ "xvcvhpsp %x0,%x1"
+ [(set_attr "type" "vecfloat")])
+
;; xscvdpsp used for splat'ing a scalar to V4SF, knowing that the internal SF
;; format of scalars is actually DF.
(define_insn "vsx_xscvdpsp_scalar"
}
[(set_attr "type" "vecperm")])
-\f
+;; Generate vector extract four float 32 values from left four elements
+;; of eight element vector of float 16 values.
+(define_expand "vextract_fp_from_shorth"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "wa")]
+ UNSPEC_VSX_VEXTRACT_FP_FROM_SHORTH))]
+ "TARGET_P9_VECTOR"
+{
+ int vals[16] = {15, 14, 0, 0, 13, 12, 0, 0, 11, 10, 0, 0, 9, 8, 0, 0};
+ int i;
+
+ rtx rvals[16];
+ rtx mask = gen_reg_rtx (V16QImode);
+ rtx tmp = gen_reg_rtx (V16QImode);
+ rtvec v;
+
+ for (i = 0; i < 16; i++)
+ rvals[i] = GEN_INT (vals[i]);
+
+ /* xvcvhpsp - vector convert F16 to vector F32 requires the four F16
+ inputs in half words 1,3,5,7 (IBM numbering). Use xxperm to move
+ src half words 0,1,2,3 for the conversion instruction. */
+ v = gen_rtvec_v (16, rvals);
+ emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
+ emit_insn (gen_altivec_vperm_v8hiv16qi (tmp, operands[1],
+ operands[1], mask));
+ emit_insn (gen_vsx_xvcvhpsp (operands[0], tmp));
+ DONE;
+})
+
+;; Generate vector extract four float 32 values from right four elements
+;; of eight element vector of float 16 values.
+(define_expand "vextract_fp_from_shortl"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "wa")]
+ UNSPEC_VSX_VEXTRACT_FP_FROM_SHORTL))]
+ "TARGET_P9_VECTOR"
+{
+ int vals[16] = {7, 6, 0, 0, 5, 4, 0, 0, 3, 2, 0, 0, 1, 0, 0, 0};
+ int i;
+ rtx rvals[16];
+ rtx mask = gen_reg_rtx (V16QImode);
+ rtx tmp = gen_reg_rtx (V16QImode);
+ rtvec v;
+
+ for (i = 0; i < 16; i++)
+ rvals[i] = GEN_INT (vals[i]);
+
+ /* xvcvhpsp - vector convert F16 to vector F32 requires the four F16
+ inputs in half words 1,3,5,7 (IBM numbering). Use xxperm to move
+ src half words 4,5,6,7 for the conversion instruction. */
+ v = gen_rtvec_v (16, rvals);
+ emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
+ emit_insn (gen_altivec_vperm_v8hiv16qi (tmp, operands[1],
+ operands[1], mask));
+ emit_insn (gen_vsx_xvcvhpsp (operands[0], tmp));
+ DONE;
+})
+
;; Support for ISA 3.0 vector byte reverse
;; Swap all bytes with in a vector
vector float vec_and (vector float, vector float);
vector float vec_and (vector float, vector bool int);
vector float vec_and (vector bool int, vector float);
+vector bool long long vec_and (vector bool long long int,
+ vector bool long long);
vector bool int vec_and (vector bool int, vector bool int);
vector signed int vec_and (vector bool int, vector signed int);
vector signed int vec_and (vector signed int, vector bool int);
vector bool char vec_sld (vector bool char,
vector bool char,
const int);
+vector bool long long int vec_sld (vector bool long long int,
+ vector bool long long int, const int);
+vector long long int vec_sld (vector long long int,
+ vector long long int, const int);
+vector unsigned long long int vec_sld (vector unsigned long long int,
+ vector unsigned long long int,
+ const int);
vector signed int vec_sll (vector signed int,
vector unsigned int);
vector unsigned short);
vector unsigned short vec_sll (vector unsigned short,
vector unsigned char);
+vector long long int vec_sll (vector long long int,
+ vector unsigned char);
+vector unsigned long long int vec_sll (vector unsigned long long int,
+ vector unsigned char);
vector bool short vec_sll (vector bool short, vector unsigned int);
vector bool short vec_sll (vector bool short, vector unsigned short);
vector bool short vec_sll (vector bool short, vector unsigned char);
vector unsigned short);
vector unsigned short vec_srl (vector unsigned short,
vector unsigned char);
+vector long long int vec_srl (vector long long int,
+ vector unsigned char);
+vector unsigned long long int vec_srl (vector unsigned long long int,
+ vector unsigned char);
vector bool short vec_srl (vector bool short, vector unsigned int);
vector bool short vec_srl (vector bool short, vector unsigned short);
vector bool short vec_srl (vector bool short, vector unsigned char);
vector signed char);
vector unsigned short vec_sro (vector unsigned short,
vector unsigned char);
+vector long long int vec_sro (vector long long int,
+ vector char);
+vector long long int vec_sro (vector long long int,
+ vector unsigned char);
+vector unsigned long long int vec_sro (vector unsigned long long int,
+ vector char);
+vector unsigned long long int vec_sro (vector unsigned long long int,
+ vector unsigned char);
vector pixel vec_sro (vector pixel, vector signed char);
vector pixel vec_sro (vector pixel, vector unsigned char);
vector signed char vec_sro (vector signed char, vector signed char);
vector signed int vec_unpackh (vector signed short);
vector bool int vec_unpackh (vector bool short);
vector unsigned int vec_unpackh (vector pixel);
+vector double vec_unpackh (vector float);
vector bool int vec_vupkhsh (vector bool short);
vector signed int vec_vupkhsh (vector signed short);
vector unsigned int vec_unpackl (vector pixel);
vector signed int vec_unpackl (vector signed short);
vector bool int vec_unpackl (vector bool short);
+vector double vec_unpackl (vector float);
vector unsigned int vec_vupklpx (vector pixel);
vector unsigned int vec_packs (vector unsigned long long,
vector unsigned long long);
+test_vsi_packsu_vssi_vssi (vector signed short x,
+
+vector unsigned char vec_packsu (vector signed short, vector signed short )
+vector unsigned char vec_packsu (vector unsigned short, vector unsigned short )
+vector unsigned short int vec_packsu (vector signed int, vector signed int);
+vector unsigned short int vec_packsu (vector unsigned int,
+ vector unsigned int);
vector unsigned int vec_packsu (vector long long, vector long long);
vector unsigned int vec_packsu (vector unsigned long long,
vector unsigned long long);
+vector unsigned int vec_packsu (vector signed long long,
+ vector signed long long);
vector long long vec_rl (vector long long,
vector unsigned long long);
vector unsigned char);
vector bool char vec_cmpne (vector bool char, vector bool char);
-vector bool short vec_cmpne (vector bool short, vector bool short);
+vector bool char vec_cmpne (vector signed char, vector signed char);
+vector bool char vec_cmpne (vector unsigned char, vector unsigned char);
vector bool int vec_cmpne (vector bool int, vector bool int);
+vector bool int vec_cmpne (vector signed int, vector signed int);
+vector bool int vec_cmpne (vector unsigned int, vector unsigned int);
vector bool long long vec_cmpne (vector bool long long, vector bool long long);
+vector bool long long vec_cmpne (vector signed long long,
+ vector signed long long);
+vector bool long long vec_cmpne (vector unsigned long long,
+ vector unsigned long long);
+vector bool short vec_cmpne (vector bool short, vector bool short);
+vector bool short vec_cmpne (vector signed short, vector signed short);
+vector bool short vec_cmpne (vector unsigned short, vector unsigned short);
+vector bool long long vec_cmpne (vector double, vector double);
+vector bool int vec_cmpne (vector float, vector float);
+
+vector float vec_extract_fp32_from_shorth (vector unsigned short);
+vector float vec_extract_fp32_from_shortl (vector unsigned short);
vector long long vec_vctz (vector long long);
vector unsigned long long vec_vctz (vector unsigned long long);
+2019-04-02 Xiong Hu Luo <luoxhu@linux.ibm.com>
+
+ Backport from trunk r250477.
+
+ 2017-07-24 Carl Love <cel@us.ibm.com>
+
+ * gcc.target/powerpc/builtins-3-p9-runnable.c: Add new test file for
+ the new built-ins.
+
+ Backport from trunk r255555.
+
+ 2017-12-11 Carl Love <cel@us.ibm.com>
+ * gcc.target/powerpc/altivec-7.c: Renamed altivec-7.h.
+ * gcc.target/powerpc/altivec-7.h (main): Add testcases for vec_unpackl.
+ Add dg-final tests for the instructions generated.
+ * gcc.target/powerpc/altivec-7-be.c: New file to test on big endian.
+ * gcc.target/powerpc/altivec-7-le.c: New file to test on little endian.
+ * gcc.target/powerpc/altivec-13.c (foo): Add vec_sld, vec_srl,
+ vec_sro testcases. Add dg-final tests for the instructions generated.
+ * gcc.target/powerpc/builtins-3-p8.c (test_vsi_packs_vui,
+ test_vsi_packs_vsi, test_vsi_packs_vssi, test_vsi_packs_vusi,
+ test_vsi_packsu-vssi, test_vsi_packsu-vusi, test_vsi_packsu-vsll,
+ test_vsi_packsu-vull, test_vsi_packsu-vsi, test_vsi_packsu-vui): Add
+ testcases. Add dg-final tests for new instructions.
+ * gcc.target/powerpc/p8vector-builtin-2.c (vbschar_eq, vbchar_eq,
+ vuchar_eq, vbint_eq, vsint_eq, viint_eq, vuint_eq, vbool_eq, vbint_ne,
+ vsint_ne, vuint_ne, vbool_ne, vsign_ne, vuns_ne, vbshort_ne): Add
+ tests.
+ Add dg-final instruction tests.
+ * gcc.target/powerpc/vsx-vector-6.c: Renamed vsx-vector-6.h.
+ * gcc.target/powerpc/vsx-vector-6.h (vec_andc,vec_nmsub, vec_nmadd,
+ vec_or, vec_nor, vec_andc, vec_or, vec_andc, vec_msums): Add tests.
+ Add dg-final tests for the generated instructions.
+ * gcc.target/powerpc/builtins-3.c (test_sll_vsc_vsc_vsuc,
+ test_sll_vuc_vuc, test_sll_vsi_vsi_vuc, test_sll_vui_vui_vuc,
+ test_sll_vbll_vull, test_sll_vbll_vbll_vus, test_sll_vp_vp_vuc,
+ test_sll_vssi_vssi_vuc, test_sll_vusi_vusi_vuc, test_slo_vsc_vsc_vsc,
+ test_slo_vuc_vuc_vsc, test_slo_vsi_vsi_vsc, test_slo_vsi_vsi_vuc,
+ test_slo_vui_vui_vsc, test_slo_vui_vui_vuc, test_slo_vsll_slo_vsll_vsc,
+ test_slo_vsll_slo_vsll_vuc, test_slo_vull_slo_vull_vsc,
+ test_slo_vull_slo_vull_vuc, test_slo_vp_vp_vsc, test_slo_vp_vp_vuc,
+ test_slo_vssi_vssi_vsc, test_slo_vssi_vssi_vuc, test_slo_vusi_vusi_vsc,
+ test_slo_vusi_vusi_vuc, test_slo_vusi_vusi_vuc, test_slo_vf_vf_vsc,
+ test_slo_vf_vf_vuc, test_cmpb_float): Add tests.
+
+ Backport from trunk r257253.
+
+ 2018-01-31 Will Schmidt <will_schmidt@vnet.ibm.com>
+
+ * gcc.target/powerpc/altivec-13.c: Remove VSX-requiring built-ins.
+ * gcc.target/powerpc/vsx-13.c: New.
+
+ Backport from trunk r258137.
+
+ 2018-03-02 Will Schmidt <will_schmidt@vnet.ibm.com>
+
+ * gcc.target/powerpc/altivec-7-be.c: Remove VSX content, allow
+ 32-bit target.
+ * gcc.target/powerpc/altivec-7.h: Remove VSX content.
+ * gcc.target/powerpc/vsx-7-be.c: New test (VSX content).
+ * gcc.target/powerpc/vsx-7.h: New include (VSX content).
+ * gcc.target/powerpc/altivec-7-le.c: Add vsx-7.h include.
+
2019-03-31 Harald Anlauf <anlauf@gmx.de>
Backport from trunk
/* { dg-do compile { target powerpc*-*-* } } */
/* { dg-require-effective-target powerpc_altivec_ok } */
/* { dg-options "-maltivec" } */
+
/* Author: Ziemowit Laski <zlaski@apple.com> */
/* This test case exercises intrinsic/argument combinations that,
while not in the Motorola AltiVec PIM, have nevertheless crept
into the AltiVec vernacular over the years. */
+/* Tests requiring VSX support (vector long long and vector double) have
+ been moved over to vsx-13.c. */
+
#include <altivec.h>
-void foo (void)
+void foo (void)
{
vector bool int boolVec1 = (vector bool int) vec_splat_u32(3);
vector bool short boolVec2 = (vector bool short) vec_splat_u16(3);
vector bool char boolVec3 = (vector bool char) vec_splat_u8(3);
-
+ vector signed char vsc1, vsc2, vscz;
+ vector unsigned char vuc1, vuc2, vucz;
+ vector signed short int vssi1, vssi2, vssiz;
+ vector signed int vsi1, vsi2, vsiz;
+ vector unsigned int vui1, vui2, vuiz;
+ vector unsigned short int vusi1, vusi2, vusiz;
+ vector pixel vp1, vp2, vpz;
+ vector float vf1, vf2, vfz;
+
boolVec1 = vec_sld( boolVec1, boolVec1, 4 );
boolVec2 = vec_sld( boolVec2, boolVec2, 2 );
boolVec3 = vec_sld( boolVec3, boolVec3, 1 );
+
+ vscz = vec_sld( vsc1, vsc2, 1 );
+ vucz = vec_sld( vuc1, vuc2, 1 );
+ vsiz = vec_sld( vsi1, vsi2, 1 );
+ vuiz = vec_sld( vui1, vui2, 1 );
+ vssiz = vec_sld( vssi1, vssi2, 1 );
+ vusiz = vec_sld( vusi1, vusi2, 1 );
+
+ vfz = vec_sld( vf1, vf2, 1 );
+
+ vpz = vec_sld( vp1, vp2, 1 );
+
+ vucz = vec_srl(vuc1, vuc2);
+ vsiz = vec_srl(vsi1, vuc2);
+ vuiz = vec_srl(vui1, vuc2);
+ vpz = vec_srl(vp1, vuc2);
+ vssiz = vec_srl(vssi1, vuc2);
+ vusiz = vec_srl(vusi1, vuc2);
+
+ vscz = vec_sro(vsc1, vsc2);
+ vscz = vec_sro(vsc1, vuc2);
+ vucz = vec_sro(vuc1, vsc2);
+ vucz = vec_sro(vuc1, vuc2);
+ vsiz = vec_sro(vsi1, vsc2);
+ vsiz = vec_sro(vsi1, vuc2);
+ vuiz = vec_sro(vui1, vsc2);
+ vuiz = vec_sro(vui1, vuc2);
+ vpz = vec_sro(vp1, vsc2);
+ vpz = vec_sro(vp1, vuc2);
+ vssiz = vec_sro(vssi1, vsc2);
+ vssiz = vec_sro(vssi1, vuc2);
+ vusiz = vec_sro(vusi1, vsc2);
+ vusiz = vec_sro(vusi1, vuc2);
+ vfz = vec_sro(vf1, vsc2);
+ vfz = vec_sro(vf1, vuc2);
}
+
+/* Expected results:
+ vec_sld vsldoi
+ vec_srl vsr
+ vec_sro vsro */
+
+/* { dg-final { scan-assembler-times "vsldoi" 11 } } */
+/* { dg-final { scan-assembler-times "vsr " 6 } } */
+/* { dg-final { scan-assembler-times "vsro" 16 } } */
--- /dev/null
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Expected results for Big Endian:
+ vec_packpx vpkpx
+ vec_ld lxvd2x
+ vec_lde lvewx
+ vec_ldl lxvl
+ vec_lvewx lvewx
+ vec_unpackh vupklsh
+ vec_unpackl vupkhsh
+ vec_andc xxnor
+ xxland
+ vec_vxor xxlxor
+ vec_vmsumubm vmsumubm
+ vec_vmulesb vmulesb
+ vec_vmulosb vmulosb
+*/
+
+/* { dg-final { scan-assembler-times "vpkpx" 2 } } */
+/* { dg-final { scan-assembler-times "vmulesb" 1 } } */
+/* { dg-final { scan-assembler-times "vmulosb" 1 } } */
+/* { dg-final { scan-assembler-times "lvewx" 2 } } */
+/* { dg-final { scan-assembler-times "lvxl" 1 } } */
+/* { dg-final { scan-assembler-times "vupklsh" 1 } } */
+/* { dg-final { scan-assembler-times "vupkhsh" 1 } } */
+
+/* Source code for the test in altivec-7.h */
+#include "altivec-7.h"
--- /dev/null
+/* { dg-do compile { target powerpc64le-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Expected results for Little Endian:
+ vec_packpx vpkpx
+ vec_vmulosb vmulesb
+ vec_ld lxv2x
+ vec_lde lvewx
+ vec_ldl lxvl
+ vec_lvewx lvewx
+ vec_unpackh vupklsh
+ vec_unpackl vupkhsh
+ vec_andc xxnor
+ xxland
+ vec_vxor xxlxor
+ vec_vmsumubm vmsumubm
+ vec_vmulesb vmulosb
+ vec_vmulosb vmulesb
+*/
+
+/* { dg-final { scan-assembler-times "vpkpx" 2 } } */
+/* { dg-final { scan-assembler-times "vmulesb" 1 } } */
+/* { dg-final { scan-assembler-times "vmulosb" 1 } } */
+/* { dg-final { scan-assembler-times "lxvd2x" 33 } } */
+/* { dg-final { scan-assembler-times "lvewx" 2 } } */
+/* { dg-final { scan-assembler-times "lvxl" 1 } } */
+/* { dg-final { scan-assembler-times "vupklsh" 1 } } */
+/* { dg-final { scan-assembler-times "vupkhsh" 1 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 0 } } */
+/* { dg-final { scan-assembler-times "xxland" 4 } } */
+/* { dg-final { scan-assembler-times "xxlxor" 5 } } */
+/* { dg-final { scan-assembler-times "vupkhpx" 1 } } */
+
+/* Source code for the test in altivec-7.h and vsx-7.h. */
+#include "altivec-7.h"
+#include "vsx-7.h"
/* Origin: Aldy Hernandez <aldyh@redhat.com> */
-/* { dg-do compile { target powerpc*-*-* } } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec" } */
+/* This test code is included into altivec-7-be.c and altivec-7-le.c.
+ The two files have the tests for the number of instructions generated for
+ LE versus BE. */
#include <altivec.h>
*vecfloat++ = vec_vxor(vecfloat[0], (vector bool int)vecint[1]);
*varpixel++ = vec_packpx(vecuint[0], vecuint[1]);
*varpixel++ = vec_vpkpx(vecuint[0], vecuint[1]);
+ *vecshort++ = vec_vmulesb(vecchar[0], vecchar[1]);
*vecshort++ = vec_vmulosb(vecchar[0], vecchar[1]);
*vecint++ = vec_ld(var_int[0], intp[1]);
*vecint++ = vec_lde(var_int[0], intp[1]);
return vec_pack (x, y);
}
+vector unsigned char
+test_vsi_packs_vusi_vusi (vector unsigned short x,
+ vector unsigned short y)
+{
+ return vec_packs (x, y);
+}
+
+vector signed char
+test_vsi_packs_vssi_vssi (vector signed short x,
+ vector signed short y)
+{
+ return vec_packs (x, y);
+}
+
+vector signed short int
+test_vsi_packs_vsi_vsi (vector signed int x,
+ vector signed int y)
+{
+ return vec_packs (x, y);
+}
+
+vector unsigned short int
+test_vsi_packs_vui_vui (vector unsigned int x,
+ vector unsigned int y)
+{
+ return vec_packs (x, y);
+}
+
vector long long
test_nabs_long_long (vector long long x)
{
return vec_packs (x, y);
}
+vector unsigned char
+test_vsi_packsu_vssi_vssi (vector signed short x,
+ vector signed short y)
+{
+ return vec_packsu (x, y);
+}
+
+vector unsigned char
+test_vsi_packsu_vusi_vusi (vector unsigned short x,
+ vector unsigned short y)
+{
+ return vec_packsu (x, y);
+}
+
+vector unsigned int
+test_vsi_packsu_vsll_vsll (vector signed long long x,
+ vector signed long long y)
+{
+ return vec_packsu (x, y);
+}
+
+vector unsigned int
+test_vsi_packsu_vull_vull (vector unsigned long long x,
+ vector unsigned long long y)
+{
+ return vec_packsu (x, y);
+}
+
+vector unsigned short int
+test_vsi_packsu_vsi_vsi (vector signed int x,
+ vector signed int y)
+{
+ return vec_packsu (x, y);
+}
+
+vector unsigned short int
+test_vsi_packsu_vui_vui (vector unsigned int x,
+ vector unsigned int y)
+{
+ return vec_packsu (x, y);
+}
+
/* Expected test results:
test_eq_long_long 1 vcmpequd inst
test_pack_float 1 vpkudum inst
test_nabs_long_long 1 vspltisw, 1 vsubudm, 1 vminsd
test_vsi_packs_vsll_vsll 1 vpksdss
- test_vui_packs_vull_vull 1 vpkudus */
+ test_vui_packs_vull_vull 1 vpkudus
+ test_vui_packs_vssi_vssi 1 vpkshss
+ test_vsi_packsu_vssi_vssi 1 vpkshus */
/* { dg-final { scan-assembler-times "vcmpequd" 1 } } */
/* { dg-final { scan-assembler-times "vpkudum" 1 } } */
/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
/* { dg-final { scan-assembler-times "vminsd" 1 } } */
/* { dg-final { scan-assembler-times "vpksdss" 1 } } */
-/* { dg-final { scan-assembler-times "vpkudus" 1 } } */
+/* { dg-final { scan-assembler-times "vpkudus" 2 } } */
+/* { dg-final { scan-assembler-times "vpkuhus" 2 } } */
+/* { dg-final { scan-assembler-times "vpkshss" 1 } } */
+/* { dg-final { scan-assembler-times "vpkshus" 1 } } */
+/* { dg-final { scan-assembler-times "vpksdus" 1 } } */
+/* { dg-final { scan-assembler-times "vpkuwus" 2 } } */
--- /dev/null
+/* { dg-do run { target { powerpc64*-*-* && { lp64 && p9vector_hw } } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+
+#include <altivec.h> // vector
+
+void abort (void);
+
+int main() {
+ int i;
+ vector float vfr, vfexpt;
+ vector unsigned short vusha;
+
+ /* 1.0, -2.0, 0.0, 8.5, 1.5, 0.5, 1.25, -0.25 */
+ vusha = (vector unsigned short){0B011110000000000, 0B1100000000000000,
+ 0B000000000000000, 0B0100100001000000,
+ 0B011111000000000, 0B0011100000000000,
+ 0B011110100000000, 0B1011010000000000};
+
+ vfexpt = (vector float){1.0, -2.0, 0.0, 8.5};
+ vfr = vec_extract_fp_from_shorth(vusha);
+
+ for (i=0; i<4; i++) {
+ if (vfr[i] != vfexpt[i])
+ abort();
+ }
+
+ vfexpt = (vector float){1.5, 0.5, 1.25, -0.25};
+ vfr = vec_extract_fp_from_shortl(vusha);
+
+ for (i=0; i<4; i++) {
+ if (vfr[i] != vfexpt[i])
+ abort();
+ }
+}
return vec_nabs (x);
}
+vector signed char
+test_sll_vsc_vsc_vsuc (vector signed char x, vector unsigned char y)
+{
+ return vec_sll (x, y);
+}
+
+vector unsigned char
+test_sll_vuc_vuc_vuc (vector unsigned char x, vector unsigned char y)
+{
+ return vec_sll (x, y);
+}
+
+vector signed int
+test_sll_vsi_vsi_vuc (vector signed int x, vector unsigned char y)
+{
+ return vec_sll (x, y);
+}
+
+vector unsigned int
+test_sll_vui_vui_vuc (vector unsigned int x, vector unsigned char y)
+{
+ return vec_sll (x, y);
+}
+
+vector bool long long
+test_sll_vbll_vbll_vuc (vector bool long long x,
+ vector unsigned char y)
+{
+ return vec_sll (x, y);
+}
+
+vector bool long long
+test_sll_vbll_vbll_vull (vector bool long long x,
+ vector unsigned long long y)
+{
+ return vec_sll (x, y);
+}
+
+vector bool long long
+test_sll_vbll_vbll_vus (vector bool long long x,
+ vector unsigned short y)
+{
+ return vec_sll (x, y);
+}
+vector pixel
+test_sll_vp_vp_vuc (vector pixel x, vector unsigned char y)
+{
+ return vec_sll (x, y);
+}
+
+vector signed short int
+test_sll_vssi_vssi_vuc (vector signed short x, vector unsigned char y)
+{
+ return vec_sll (x, y);
+}
+
+vector unsigned short int
+test_sll_vusi_vusi_vuc (vector unsigned short x, vector unsigned char y)
+{
+ return vec_sll (x, y);
+}
+
+vector signed char
+test_slo_vsc_vsc_vsc (vector signed char x, vector signed char y)
+{
+ return vec_slo (x, y);
+}
+
+vector signed char
+test_slo_vsc_vsc_vuc (vector signed char x, vector unsigned char y)
+{
+ return vec_slo (x, y);
+}
+
+vector unsigned char
+test_slo_vuc_vuc_vsc (vector unsigned char x, vector signed char y)
+{
+ return vec_slo (x, y);
+}
+
+vector unsigned char
+test_slo_vuc_vuc_vuc (vector unsigned char x, vector unsigned char y)
+{
+ return vec_slo (x, y);
+}
+
+vector signed int
+test_slo_vsi_vsi_vsc (vector signed int x, vector signed char y)
+{
+ return vec_slo (x, y);
+}
+
+vector signed int
+test_slo_vsi_vsi_vuc (vector signed int x, vector unsigned char y)
+{
+ return vec_slo (x, y);
+}
+
+vector unsigned int
+test_slo_vui_vui_vsc (vector unsigned int x, vector signed char y)
+{
+ return vec_slo (x, y);
+}
+
+vector unsigned int
+test_slo_vui_vui_vuc (vector unsigned int x, vector unsigned char y)
+{
+ return vec_slo (x, y);
+}
+
+vector pixel
+test_slo_vp_vp_vsc (vector pixel int x, vector signed char y)
+{
+ return vec_slo (x, y);
+}
+
+vector pixel
+test_slo_vp_vp_vuc (vector pixel int x, vector unsigned char y)
+{
+ return vec_slo (x, y);
+}
+
+vector signed short int
+test_slo_vssi_vssi_vsc (vector signed short int x, vector signed char y)
+{
+ return vec_slo (x, y);
+}
+
+vector signed short int
+test_slo_vssi_vssi_vuc (vector signed short int x, vector unsigned char y)
+{
+ return vec_slo (x, y);
+}
+
+vector unsigned short int
+test_slo_vusi_vusi_vsc (vector unsigned short int x, vector signed char y)
+{
+ return vec_slo (x, y);
+}
+
+vector unsigned short int
+test_slo_vusi_vusi_vuc (vector unsigned short int x, vector unsigned char y)
+{
+ return vec_slo (x, y);
+}
+
+vector float
+test_slo_vf_vf_vsc (vector float x, vector signed char y)
+{
+ return vec_slo (x, y);
+}
+
+vector float
+test_slo_vf_vf_vuc (vector float x, vector unsigned char y)
+ {
+ return vec_slo (x, y);
+ }
+
+vector int
+test_cmpb_float (vector float x, vector float y)
+{
+ return vec_cmpb (x, y);
+}
+
/* Expected test results:
test_eq_char 1 vcmpequb inst
test_nabs_short 1 vspltisw, 1 vsubuhm, 1 vminsh
test_nabs_int 1 vspltisw, 1 vsubuwm, 1 vminsw
test_nabs_float 1 xvnabssp
- test_nabs_double 1 xvnabsdp */
+ test_nabs_double 1 xvnabsdp
+ test_cmpb_float 1 vcmpbfp */
/* { dg-final { scan-assembler-times "vcmpequb" 1 } } */
/* { dg-final { scan-assembler-times "vcmpequh" 1 } } */
/* { dg-final { scan-assembler-times "vspltisw" 3 } } */
/* { dg-final { scan-assembler-times "xvnabssp" 1 } } */
/* { dg-final { scan-assembler-times "xvnabsdp" 1 } } */
+/* { dg-final { scan-assembler-times "vcmpbfp" 1 } } */
typedef vector long long v_sign;
typedef vector unsigned long long v_uns;
typedef vector bool long long v_bool;
+typedef vector bool char v_bchar;
+typedef vector bool int v_bint;
+typedef vector bool short v_bshort;
+typedef vector signed int v_sint;
+typedef vector unsigned int v_uint;
+typedef vector signed char v_schar;
+typedef vector unsigned char v_uchar;
+typedef vector float v_float;
v_sign sign_add_1 (v_sign a, v_sign b)
{
return vec_vsrad (a, b);
}
+v_bchar vbchar_eq (v_bchar a, v_bchar b)
+{
+ return vec_cmpeq (a, b);
+}
+
+v_bchar vbschar_eq (v_schar a, v_schar b)
+{
+ return vec_cmpeq (a, b);
+}
+
+v_bchar vuchar_eq (v_uchar a, v_uchar b)
+{
+ return vec_cmpeq (a, b);
+}
+
+v_bint vbint_eq (v_bint a, v_bint b)
+{
+ return vec_cmpeq (a, b);
+}
+
+v_bint vsint_eq (v_sint a, v_sint b)
+{
+ return vec_cmpeq (a, b);
+}
+
+v_bint vuint_eq (v_uint a, v_uint b)
+{
+ return vec_cmpeq (a, b);
+}
+
+v_bool vbool_eq (v_bool a, v_bool b)
+{
+ return vec_cmpeq (a, b);
+}
+
+v_bint vbint_ne (v_bint a, v_bint b)
+{
+ return vec_cmpne (a, b);
+}
+
+v_bint vsint_ne (v_sint a, v_sint b)
+{
+ return vec_cmpne (a, b);
+}
+
+v_bint vuint_ne (v_uint a, v_uint b)
+{
+ return vec_cmpne (a, b);
+}
+
+v_bool vbool_ne (v_bool a, v_bool b)
+{
+ return vec_cmpne (a, b);
+}
+
+v_bool vsign_ne (v_sign a, v_sign b)
+{
+ return vec_cmpne (a, b);
+}
+
+v_bool vuns_ne (v_uns a, v_uns b)
+{
+ return vec_cmpne (a, b);
+}
+
+v_bshort vbshort_ne (v_bshort a, v_bshort b)
+{
+ return vec_cmpne (a, b);
+}
+
+
/* { dg-final { scan-assembler-times "vaddudm" 5 } } */
/* { dg-final { scan-assembler-times "vsubudm" 6 } } */
/* { dg-final { scan-assembler-times "vmaxsd" 4 } } */
/* { dg-final { scan-assembler-times "vminsd" 3 } } */
/* { dg-final { scan-assembler-times "vmaxud" 2 } } */
/* { dg-final { scan-assembler-times "vminud" 2 } } */
-/* { dg-final { scan-assembler-times "vcmpequd" 2 } } */
+/* { dg-final { scan-assembler-times "vcmpequd" 6 } } */
/* { dg-final { scan-assembler-times "vcmpgtsd" 1 } } */
/* { dg-final { scan-assembler-times "vcmpgtud" 1 } } */
/* { dg-final { scan-assembler-times "vrld" 3 } } */
/* { dg-final { scan-assembler-times "vsld" 5 } } */
/* { dg-final { scan-assembler-times "vsrad" 3 } } */
+/* { dg-final { scan-assembler-times "vcmpequb" 3 } } */
+/* { dg-final { scan-assembler-times "vcmpequw" 6 } } */
--- /dev/null
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx" } */
+
+/* Variations of tests that require VSX support. This is a variation of
+ the altivec-13.c testcase. */
+
+#include <altivec.h>
+
+void foo (void)
+{
+
+ vector signed char vsc1, vsc2, vscz;
+ vector unsigned char vuc1, vuc2, vucz;
+ vector bool long long vubll1, vubll2, vubllz;
+ vector signed int long long vsill1, vsill2, vsillz;
+ vector unsigned int long long vuill1, vuill2, vuillz;
+ vector double vd1, vd2, vdz;
+
+ vubllz = vec_sld( vubll1, vubll2, 1 );
+ vsillz = vec_sld( vsill1, vsill2, 1 );
+ vuillz = vec_sld( vuill1, vuill2, 1 );
+
+ vsillz = vec_srl(vsill1, vuc2);
+ vuillz = vec_srl(vuill1, vuc2);
+
+ vsillz = vec_sro(vsill1, vsc2);
+ vsillz = vec_sro(vsill1, vuc2);
+ vuillz = vec_sro(vuill1, vsc2);
+ vuillz = vec_sro(vuill1, vuc2);
+
+ vdz = vec_sld( vd1, vd2, 1 );
+}
+
+/* Expected results:
+ vec_sld vsldoi
+ vec_srl vsr
+ vec_sro vsro */
+
+/* { dg-final { scan-assembler-times "vsldoi" 4 } } */
+/* { dg-final { scan-assembler-times "vsr " 2 } } */
+/* { dg-final { scan-assembler-times "vsro" 4 } } */
--- /dev/null
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx" } */
+
+/* This is an extension of altivec-7-be.c, with vsx target features included. */
+
+/* Expected results for Big Endian:
+(from altivec-7.h)
+ vec_packpx vpkpx
+ vec_ld lxvd2x or lxv
+ vec_lde lvewx
+ vec_ldl lxvl
+ vec_lvewx lvewx
+ vec_andc xxnor
+ xxland
+ vec_vxor xxlxor
+ vec_vmsumubm vmsumubm
+ vec_vmulesb vmulesb
+ vec_vmulosb vmulosb
+(from vsx-7.h)
+ vec_unpackl vupkhsh
+ vec_unpackh vupklsh
+*/
+
+/* { dg-final { scan-assembler-times "vpkpx" 2 } } */
+/* { dg-final { scan-assembler-times "vmulesb" 1 } } */
+/* { dg-final { scan-assembler-times "vmulosb" 1 } } */
+
+// For LE platforms P9 and later, we generate the lxv insn instead of lxvd2x.
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 0 { target { { powerpc64*le-*-* } && { p9vector_hw } } } } } */
+/* { dg-final { scan-assembler-times {\mlxv\M} 36 { target { { powerpc64*le-*-* } && { p9vector_hw } } } } } */
+// For LE platforms < P9.
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 33 { target { { powerpc64*le-*-* } && { ! p9vector_hw } } } } } */
+// For BE platforms we generate 6 lxvd2x insns.
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 6 { target { { ! powerpc64*le-*-* } && { ! p9vector_hw } } } } } */
+
+/* { dg-final { scan-assembler-times "lvewx" 2 } } */
+/* { dg-final { scan-assembler-times "lvxl" 1 } } */
+/* { dg-final { scan-assembler-times "vupklsh" 1 } } */
+/* { dg-final { scan-assembler-times "vupkhsh" 1 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 0 } } */
+/* { dg-final { scan-assembler-times "xxland" 4 } } */
+/* { dg-final { scan-assembler-times "xxlxor" 5 } } */
+/* { dg-final { scan-assembler-times "vupkhpx" 1 } } */
+
+/* Source code for the 'altivec' test in altivec-7.h */
+/* Source code for the 'vsx' required tests in vsx-7.h */
+
+#include "altivec-7.h"
+#include "vsx-7.h"
--- /dev/null
+
+/* This test code is included into vsx-7-be.c.
+ * this is meant to supplement code in altivec-7.h. */
+
+#include <altivec.h>
+
+
+vector float *vecfloat;
+vector double *vecdouble;
+
+int main2 ()
+{
+
+ *vecdouble++ = vec_unpackl(vecfloat[0]);
+ *vecdouble++ = vec_unpackh(vecfloat[0]);
+
+ return 0;
+}
--- /dev/null
+/* { dg-do compile { target { powerpc64-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
+
+/* Expected instruction counts for Big Endian */
+
+/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvadddp" 1 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 7 } } */
+/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 } } */
+/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 } } */
+/* { dg-final { scan-assembler-times "xvcmpgedp" 6 } } */
+/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */
+/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */
+/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmindp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */
+/* { dg-final { scan-assembler-times "vperm" 1 } } */
+/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */
+/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */
+/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */
+/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */
+/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */
+/* { dg-final { scan-assembler-times "xxland" 13 } } */
+
+/* Source code for the test in vsx-vector-6.h */
+#include "vsx-vector-6.h"
--- /dev/null
+/* { dg-do compile { target { powerpc64le-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
+
+/* Expected instruction counts for Little Endian */
+
+/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvadddp" 1 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 6 } } */
+/* { dg-final { scan-assembler-times "xxlor" 14 } } */
+/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 } } */
+/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 } } */
+/* { dg-final { scan-assembler-times "xvcmpgedp" 6 } } */
+/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */
+/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */
+/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmindp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */
+/* { dg-final { scan-assembler-times "vperm" 1 } } */
+/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */
+/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */
+/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */
+/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */
+/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */
+/* { dg-final { scan-assembler-times "xxland" 9 } } */
+
+/* Source code for the test in vsx-vector-6.h */
+#include "vsx-vector-6.h"
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-mvsx -O2" } */
+/* This test code is included into vsx-vector-6-be.c and vsx-vector-6-le.c.
+ The two files have the tests for the number of instructions generated for
+ LE versus BE. */
#include <altivec.h>
-void foo (vector double *out, vector double *in, vector long *p_l, vector bool long *p_b, vector unsigned char *p_uc, int *i)
+void foo (vector double *out, vector double *in, vector long *p_l, vector bool long *p_b,
+ vector unsigned char *p_uc, int *i, vector float *p_f,
+ vector bool char *outbc, vector bool int *outbi,
+ vector bool short *outbsi, vector int *outsi, vector unsigned int *outui)
{
vector double in0 = in[0];
vector double in1 = in[1];
vector double in2 = in[2];
vector long inl = *p_l;
vector bool long inb = *p_b;
+ vector bool long long inbl0;
+ vector bool long long inbl1;
vector unsigned char uc = *p_uc;
-
+ vector float inf0;
+ vector float inf1;
+ vector float inf2;
+ vector bool char inbc0;
+ vector bool char inbc1;
+ vector bool short inbs0;
+ vector bool short inbs1;
+ vector bool int inbi0;
+ vector bool int inbi1;
+ vector signed short int inssi0, inssi1;
+ vector unsigned short int inusi0, inusi1;
+ vector signed int insi0, insi1;
+ vector unsigned int inui0, inui1;
+
*out++ = vec_abs (in0);
*out++ = vec_add (in0, in1);
*out++ = vec_and (in0, in1);
*out++ = vec_andc (in0, in1);
*out++ = vec_andc (in0, inb);
*out++ = vec_andc (inb, in0);
+ *out++ = vec_andc (inbl0, in0);
+ *out++ = vec_andc (in0, inbl0);
+
*out++ = vec_ceil (in0);
*p_b++ = vec_cmpeq (in0, in1);
*p_b++ = vec_cmpgt (in0, in1);
*i++ = vec_any_nle (in0, in1);
*i++ = vec_any_nlt (in0, in1);
*i++ = vec_any_numeric (in0);
+
+ *p_f++ = vec_msub (inf0, inf1, inf2);
+ *p_f++ = vec_nmsub (inf0, inf1, inf2);
+ *p_f++ = vec_nmadd (inf0, inf1, inf2);
+ *p_f++ = vec_or (inf0, inf1);
+
+ *out++ = vec_or (inbl0, in0);
+ *out++ = vec_or (in0, inbl0);
+
+ *out++ = vec_nor (in0, in1);
+
+ *outbc++ = vec_nor (inbc0, inbc1);
+ *outbc++ = vec_andc (inbc0, inbc1);
+ *outbc++ = vec_or (inbc0, inbc1);
+
+ *outbi++ = vec_andc (inbi0, inbi1);
+ *outbsi++ = vec_andc (inbs0, inbs1);
+
+ *outbsi++ = vec_andc (inbs0, inbs1);
+
+ *outbi++ = vec_nor (inbi0, inbi1);
+ *outbi++ = vec_or (inbi0, inbi1);
+
+ *outbsi++ = vec_nor (inbs0, inbs1);
+ *outbsi++ = vec_or (inbs0, inbs1);
+
+ *outsi++ = vec_msums(inssi0, inssi1, insi0);
+ *outui++ = vec_msums(inusi0, inusi1, inui0);
+
+ *p_f++ = vec_nor (inf0, inf1);
+
+ *p_f++ = vec_andc (inf0, inf1);
+ *p_f++ = vec_andc (inbi0, inf0);
+ *p_f++ = vec_andc (inf0, inbi0);
+
+ *in++ = vec_andc (inbl0, in1);
+ *in++ = vec_andc (in0, inbl1);
+}
+
+int main()
+{
+ vector double *out;
+ vector double *in;
+ vector long *p_l;
+ vector bool long *p_b;
+ vector unsigned char *p_uc;
+ int *i;
+ vector float *p_f;
+ vector bool char *outbc;
+ vector bool int *outbi;
+ vector bool short *outbsi;
+ vector int *outsi;
+ vector unsigned int *outui;
+
+ foo (out, in, p_l, p_b, p_uc, i, p_f, outbc,
+ outbi, outbsi, outsi, outui);
}
projects / thirdparty / gcc.git / commitdiff
