riscv: dts: sophgo: sg2044: Add "b" ISA extension

"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs
(Jun/2021). With "b" added into riscv/extensions.yaml, a dependency
checking rule is now enforced, which requires that when zba, zbb, and zbs
are all specified, "b" must be added as well. Failing to do this will
cause dtbs_check schema check warnings.

According to uabi.rst, as a single-letter extension, "b" should be added
after "c" in canonical order.

Update sg2044-cpus.dtsi to conform to this rule.

Signed-off-by: Guodong Xu <guodong@riscstar.com>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-3-254dd61cf947@riscstar.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>

diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
index 523799a1a8b821dceb476e8bdc16e5c372e04d09..3135409c21492fc69766e6205ac3ab2b571a8718 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
@@ -24,10 +24,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache0>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -60,10 +60,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache0>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -96,10 +96,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache0>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -132,10 +132,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache0>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -168,10 +168,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache1>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -204,10 +204,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache1>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -240,10 +240,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache1>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -276,10 +276,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache1>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -312,10 +312,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache2>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -348,10 +348,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache2>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -384,10 +384,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache2>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -420,10 +420,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache2>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -456,10 +456,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache3>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -492,10 +492,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache3>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -528,10 +528,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache3>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -564,10 +564,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache3>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -600,10 +600,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache4>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -636,10 +636,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache4>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -672,10 +672,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache4>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -708,10 +708,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache4>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -744,10 +744,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache5>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -780,10 +780,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache5>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -816,10 +816,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache5>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -852,10 +852,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache5>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -888,10 +888,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache6>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -924,10 +924,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache6>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -960,10 +960,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache6>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -996,10 +996,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache6>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1032,10 +1032,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache7>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1068,10 +1068,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache7>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1104,10 +1104,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache7>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1140,10 +1140,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache7>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1176,10 +1176,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache8>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1212,10 +1212,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache8>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1248,10 +1248,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache8>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1284,10 +1284,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache8>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1320,10 +1320,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache9>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1356,10 +1356,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache9>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1392,10 +1392,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache9>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1428,10 +1428,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache9>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1464,10 +1464,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache10>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1500,10 +1500,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache10>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1536,10 +1536,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache10>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1572,10 +1572,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache10>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1608,10 +1608,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache11>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1644,10 +1644,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache11>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1680,10 +1680,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache11>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1716,10 +1716,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache11>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1752,10 +1752,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache12>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1788,10 +1788,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache12>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1824,10 +1824,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache12>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1860,10 +1860,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache12>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1896,10 +1896,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache13>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1932,10 +1932,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache13>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -1968,10 +1968,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache13>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -2004,10 +2004,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache13>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -2040,10 +2040,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache14>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -2076,10 +2076,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache14>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -2112,10 +2112,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache14>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -2148,10 +2148,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache14>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -2184,10 +2184,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache15>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -2220,10 +2220,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache15>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -2256,10 +2256,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache15>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",
@@ -2292,10 +2292,10 @@
                        device_type = "cpu";
                        mmu-type = "riscv,sv48";
                        next-level-cache = <&l2_cache15>;
-                       riscv,isa = "rv64imafdcv";
+                       riscv,isa = "rv64imafdcbv";
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-                                              "v", "sscofpmf", "sstc",
+                                              "b", "v", "sscofpmf", "sstc",
                                               "svinval", "svnapot", "svpbmt",
                                               "zawrs", "zba", "zbb", "zbc",
                                               "zbs", "zca", "zcb", "zcd",