ARM: dts: renesas: rcar-gen2: Add boot phase tags

bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to describe various node usage during
boot phases with DT.  Add bootph-all for all nodes that are used in the
bootloader on Renesas R-Car Gen2 SoCs.

All SoC require CPG clock and its input clock, RST Reset, PFC pin
control and PRR ID register access during all stages of the boot
process, those are marked using bootph-all property, and so is the SoC
bus node which contains these IP.

Each board console UART is also marked as bootph-all to make it
available in all stages of the boot process.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250209180616.160253-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm/boot/dts/renesas/r8a7790-lager.dts b/arch/arm/boot/dts/renesas/r8a7790-lager.dts
index 3bce5876a9d81aac6c05336df0c9c93db148e18c..4f002aa7fbafc5cfdcb8d97b30083e4fca0d6dab 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/renesas/r8a7790-lager.dts
@@ -754,6 +754,7 @@
 &scif0 {
        pinctrl-0 = <&scif0_pins>;
        pinctrl-names = "default";
+       bootph-all;
 
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/renesas/r8a7790-stout.dts b/arch/arm/boot/dts/renesas/r8a7790-stout.dts
index d7c0a9574ce83144f134311d8980953290ee82cf..b1e20579e071096cc37353cf934fabec0735f678 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7790-stout.dts
+++ b/arch/arm/boot/dts/renesas/r8a7790-stout.dts
@@ -268,6 +268,7 @@
 &scifa0 {
        pinctrl-0 = <&scifa0_pins>;
        pinctrl-names = "default";
+       bootph-all;
 
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/renesas/r8a7790.dtsi b/arch/arm/boot/dts/renesas/r8a7790.dtsi
index f746f0b9e686bb49e98a62c64a5f83fed1192c6a..4f97c09dbc9fe95793fdab1f95ef65ae42748da0 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7790.dtsi
+++ b/arch/arm/boot/dts/renesas/r8a7790.dtsi
@@ -227,6 +227,7 @@
                #clock-cells = <0>;
                /* This value must be overridden by the board. */
                clock-frequency = <0>;
+               bootph-all;
        };
 
        /* External PCIe clock - can be overridden by the board */
@@ -265,6 +266,7 @@
        soc {
                compatible = "simple-bus";
                interrupt-parent = <&gic>;
+               bootph-all;
 
                #address-cells = <2>;
                #size-cells = <2>;
@@ -374,6 +376,7 @@
                pfc: pinctrl@e6060000 {
                        compatible = "renesas,pfc-r8a7790";
                        reg = <0 0xe6060000 0 0x250>;
+                       bootph-all;
                };
 
                tpu: pwm@e60f0000 {
@@ -395,6 +398,7 @@
                        #clock-cells = <2>;
                        #power-domain-cells = <0>;
                        #reset-cells = <1>;
+                       bootph-all;
                };
 
                apmu@e6151000 {
@@ -412,6 +416,7 @@
                rst: reset-controller@e6160000 {
                        compatible = "renesas,r8a7790-rst";
                        reg = <0 0xe6160000 0 0x0100>;
+                       bootph-all;
                };
 
                sysc: system-controller@e6180000 {
@@ -1948,6 +1953,7 @@
                prr: chipid@ff000044 {
                        compatible = "renesas,prr";
                        reg = <0 0xff000044 0 4>;
+                       bootph-all;
                };
 
                cmt0: timer@ffca0000 {
@@ -2018,5 +2024,6 @@
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <48000000>;
+               bootph-all;
        };
 };

diff --git a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts
index e4e1d9c98c617883cfc04ed5f9a95e8ec379fd59..e9f90fa44d551be29622973baec25dbf89a8d36c 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts
@@ -679,6 +679,7 @@
 &scif0 {
        pinctrl-0 = <&scif0_pins>;
        pinctrl-names = "default";
+       bootph-all;
 
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/renesas/r8a7791-porter.dts b/arch/arm/boot/dts/renesas/r8a7791-porter.dts
index 08381498350aacde48856b83966ce47e9e78850f..f518eadd8b9cdad310cb54d79d84131623ee25ca 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/renesas/r8a7791-porter.dts
@@ -312,6 +312,7 @@
 &scif0 {
        pinctrl-0 = <&scif0_pins>;
        pinctrl-names = "default";
+       bootph-all;
 
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/renesas/r8a7791.dtsi b/arch/arm/boot/dts/renesas/r8a7791.dtsi
index e57567adff558844c3dfc4d27278879e7ab7acda..5023b41c28b361730eb5bf87805867e8320c0ffa 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7791.dtsi
+++ b/arch/arm/boot/dts/renesas/r8a7791.dtsi
@@ -125,6 +125,7 @@
                #clock-cells = <0>;
                /* This value must be overridden by the board. */
                clock-frequency = <0>;
+               bootph-all;
        };
 
        /* External PCIe clock - can be overridden by the board */
@@ -152,6 +153,7 @@
        soc {
                compatible = "simple-bus";
                interrupt-parent = <&gic>;
+               bootph-all;
 
                #address-cells = <2>;
                #size-cells = <2>;
@@ -291,6 +293,7 @@
                pfc: pinctrl@e6060000 {
                        compatible = "renesas,pfc-r8a7791";
                        reg = <0 0xe6060000 0 0x250>;
+                       bootph-all;
                };
 
                tpu: pwm@e60f0000 {
@@ -312,6 +315,7 @@
                        #clock-cells = <2>;
                        #power-domain-cells = <0>;
                        #reset-cells = <1>;
+                       bootph-all;
                };
 
                apmu@e6152000 {
@@ -323,6 +327,7 @@
                rst: reset-controller@e6160000 {
                        compatible = "renesas,r8a7791-rst";
                        reg = <0 0xe6160000 0 0x0100>;
+                       bootph-all;
                };
 
                sysc: system-controller@e6180000 {
@@ -1875,6 +1880,7 @@
                prr: chipid@ff000044 {
                        compatible = "renesas,prr";
                        reg = <0 0xff000044 0 4>;
+                       bootph-all;
                };
 
                cmt0: timer@ffca0000 {
@@ -1945,5 +1951,6 @@
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <48000000>;
+               bootph-all;
        };
 };

diff --git a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts
index a3986076d8e3e99373a4b1f4bb5ce59b46a75ab5..23ec0f8a6651083441ee4252f287a0bc0ecc8c8a 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts
+++ b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts
@@ -301,6 +301,7 @@
 &scif0 {
        pinctrl-0 = <&scif0_pins>;
        pinctrl-names = "default";
+       bootph-all;
 
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/renesas/r8a7792-wheat.dts b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts
index bfc780f7e396b4087b0530a73ccc6c987e565b7c..93bd81723c8fb4b6178c7aff6c53b1a7222bf420 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7792-wheat.dts
+++ b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts
@@ -183,6 +183,7 @@
 &scif0 {
        pinctrl-0 = <&scif0_pins>;
        pinctrl-names = "default";
+       bootph-all;
 
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/renesas/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi
index 08cbe6c13cee46567fc7d58a140c57d91ae20400..7513afc1c95853eaeffe899838cb22e76cdce08d 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7792.dtsi
+++ b/arch/arm/boot/dts/renesas/r8a7792.dtsi
@@ -82,6 +82,7 @@
                #clock-cells = <0>;
                /* This value must be overridden by the board. */
                clock-frequency = <0>;
+               bootph-all;
        };
 
        lbsc: bus {
@@ -109,6 +110,7 @@
        soc {
                compatible = "simple-bus";
                interrupt-parent = <&gic>;
+               bootph-all;
 
                #address-cells = <2>;
                #size-cells = <2>;
@@ -308,6 +310,7 @@
                pfc: pinctrl@e6060000 {
                        compatible = "renesas,pfc-r8a7792";
                        reg = <0 0xe6060000 0 0x144>;
+                       bootph-all;
                };
 
                cpg: clock-controller@e6150000 {
@@ -318,6 +321,7 @@
                        #clock-cells = <2>;
                        #power-domain-cells = <0>;
                        #reset-cells = <1>;
+                       bootph-all;
                };
 
                apmu@e6152000 {
@@ -329,6 +333,7 @@
                rst: reset-controller@e6160000 {
                        compatible = "renesas,r8a7792-rst";
                        reg = <0 0xe6160000 0 0x0100>;
+                       bootph-all;
                };
 
                sysc: system-controller@e6180000 {
@@ -947,6 +952,7 @@
                prr: chipid@ff000044 {
                        compatible = "renesas,prr";
                        reg = <0 0xff000044 0 4>;
+                       bootph-all;
                };
 
                cmt0: timer@ffca0000 {

diff --git a/arch/arm/boot/dts/renesas/r8a7793-gose.dts b/arch/arm/boot/dts/renesas/r8a7793-gose.dts
index 2c05d7c2b37765251357768bca81b9626e6c7d8f..45b267ec267943759d1deccac97c29b9b4b51acf 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/renesas/r8a7793-gose.dts
@@ -642,6 +642,7 @@
 &scif0 {
        pinctrl-0 = <&scif0_pins>;
        pinctrl-names = "default";
+       bootph-all;
 
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/renesas/r8a7793.dtsi b/arch/arm/boot/dts/renesas/r8a7793.dtsi
index e48e43cc6b03d8c81c4a62506c07b0b721a4377c..fc6d3bcca2961f8e17a2f53a3bda819e0506be70 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7793.dtsi
+++ b/arch/arm/boot/dts/renesas/r8a7793.dtsi
@@ -117,6 +117,7 @@
                #clock-cells = <0>;
                /* This value must be overridden by the board. */
                clock-frequency = <0>;
+               bootph-all;
        };
 
        pmu {
@@ -137,6 +138,7 @@
        soc {
                compatible = "simple-bus";
                interrupt-parent = <&gic>;
+               bootph-all;
 
                #address-cells = <2>;
                #size-cells = <2>;
@@ -276,6 +278,7 @@
                pfc: pinctrl@e6060000 {
                        compatible = "renesas,pfc-r8a7793";
                        reg = <0 0xe6060000 0 0x250>;
+                       bootph-all;
                };
 
                /* Special CPG clocks */
@@ -287,6 +290,7 @@
                        #clock-cells = <2>;
                        #power-domain-cells = <0>;
                        #reset-cells = <1>;
+                       bootph-all;
                };
 
                apmu@e6152000 {
@@ -298,6 +302,7 @@
                rst: reset-controller@e6160000 {
                        compatible = "renesas,r8a7793-rst";
                        reg = <0 0xe6160000 0 0x0100>;
+                       bootph-all;
                };
 
                sysc: system-controller@e6180000 {
@@ -1454,6 +1459,7 @@
                prr: chipid@ff000044 {
                        compatible = "renesas,prr";
                        reg = <0 0xff000044 0 4>;
+                       bootph-all;
                };
 
                cmt0: timer@ffca0000 {
@@ -1524,5 +1530,6 @@
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <48000000>;
+               bootph-all;
        };
 };

diff --git a/arch/arm/boot/dts/renesas/r8a7794-alt.dts b/arch/arm/boot/dts/renesas/r8a7794-alt.dts
index f70e26aa83a0a4d3e06c0595d1d37237ec800ce6..3f06a7f67d62ad6b31e465a7fa29029269c44394 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/renesas/r8a7794-alt.dts
@@ -479,6 +479,7 @@
 &scif2 {
        pinctrl-0 = <&scif2_pins>;
        pinctrl-names = "default";
+       bootph-all;
 
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/renesas/r8a7794-silk.dts b/arch/arm/boot/dts/renesas/r8a7794-silk.dts
index 2a0819311a3c4ef3d6cc87e34909d3a92347d9fa..342825605768037d50f140aca0fa24887e497ca4 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/renesas/r8a7794-silk.dts
@@ -394,6 +394,7 @@
 &scif2 {
        pinctrl-0 = <&scif2_pins>;
        pinctrl-names = "default";
+       bootph-all;
 
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/renesas/r8a7794.dtsi b/arch/arm/boot/dts/renesas/r8a7794.dtsi
index bc16c896c0f9b94a25a319ea5d20aa24fb3a63e6..92010d09f6c40aa00f941003fc9194fed1877a3d 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7794.dtsi
+++ b/arch/arm/boot/dts/renesas/r8a7794.dtsi
@@ -99,6 +99,7 @@
                #clock-cells = <0>;
                /* This value must be overridden by the board. */
                clock-frequency = <0>;
+               bootph-all;
        };
 
        pmu {
@@ -119,6 +120,7 @@
        soc {
                compatible = "simple-bus";
                interrupt-parent = <&gic>;
+               bootph-all;
 
                #address-cells = <2>;
                #size-cells = <2>;
@@ -243,6 +245,7 @@
                pfc: pinctrl@e6060000 {
                        compatible = "renesas,pfc-r8a7794";
                        reg = <0 0xe6060000 0 0x11c>;
+                       bootph-all;
                };
 
                cpg: clock-controller@e6150000 {
@@ -253,6 +256,7 @@
                        #clock-cells = <2>;
                        #power-domain-cells = <0>;
                        #reset-cells = <1>;
+                       bootph-all;
                };
 
                apmu@e6151000 {
@@ -264,6 +268,7 @@
                rst: reset-controller@e6160000 {
                        compatible = "renesas,r8a7794-rst";
                        reg = <0 0xe6160000 0 0x0100>;
+                       bootph-all;
                };
 
                sysc: system-controller@e6180000 {
@@ -1440,6 +1445,7 @@
                prr: chipid@ff000044 {
                        compatible = "renesas,prr";
                        reg = <0 0xff000044 0 4>;
+                       bootph-all;
                };
 
                cmt0: timer@ffca0000 {
@@ -1491,5 +1497,6 @@
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <48000000>;
+               bootph-all;
        };
 };