BASE_ARCH_END
};
-/* Architecture specific propoerties. */
+/* Architecture specific properties. */
typedef struct
{
FLAGS Specific hardware flags that are enabled by this CPU configuration,
as defined in arc-options.def file, and allowed by arc-arches.def
file. The specific hardware flags are enumerated without using
- spaces between the '|' character and consequtive flags.
+ spaces between the '|' character and consecutive flags.
EXTRA Extra hardware flags, different than the ones in
arc-arches.def. Here we can specify the width of lp_count,
for example.
static arc_jli_section *arc_jli_sections = NULL;
-/* Track which regs are set fixed/call saved/call used from commnad line. */
+/* Track which regs are set fixed/call saved/call used from command line. */
HARD_REG_SET overrideregs;
/* Maximum size of a loop. */
return false;
}
- /* Scalled addresses for sdata is done other places. */
+ /* Scaled addresses for sdata is done other places. */
if (legitimate_small_data_address_p (op, mode))
return false;
return (42);
}
-/* Return true if COMPARISON has a short form that can accomodate OFFSET. */
+/* Return true if COMPARISON has a short form that can accommodate OFFSET. */
bool
arc_short_comparison_p (rtx comparison, int offset)
}
}
-/* Return TRUE if reg is ok for short instrcutions. */
+/* Return TRUE if reg is ok for short instructions. */
static bool
arc_check_short_reg_p (rtx op)
return GET_MODE_SIZE (GET_MODE (reg));
}
-/* Check if we have a continous range to be save/restored with the
- help of enter/leave instructions. A vaild register range starts
+/* Check if we have a continuous range to be save/restored with the
+ help of enter/leave instructions. A valid register range starts
from $r13 and is up to (including) $r26. */
static bool
if (offset && !restore_fp)
{
- /* This add is only emmited when we do not restore fp with leave
+ /* This add is only emitted when we do not restore fp with leave
instruction. */
frame_stack_add (offset);
frame_allocated += offset;
that no executable code but trampolines is on the stack, no icache
entries linger for the area of the stack from when before the stack
was allocated, and allocating trampolines in trampoline-only cache
- lines or allocate trampolines fram a special pool of pre-allocated
+ lines or allocate trampolines from a special pool of pre-allocated
trampolines. */
static void
arc_jli_sections = new_section;
}
-/* This is set briefly to 1 when we output a ".as" address modifer, and then
+/* This is set briefly to 1 when we output a ".as" address modifier, and then
reset when we output the scaled address. */
static int output_scaled = 0;
return NULL;
}
-/* Return the next active insn, skiping the inline assembly code. */
+/* Return the next active insn, skipping the inline assembly code. */
static rtx_insn *
arc_active_insn (rtx_insn *insn)
delay slot scheduling:
- If a delay slot is filled with a nocond/set insn from above, the previous
- basic block can become elegible for conditional execution.
+ basic block can become eligible for conditional execution.
- If a delay slot is filled with a nocond insn from the fall-through path,
- the branch with that delay slot can become eligble for conditional
+ the branch with that delay slot can become eligible for conditional
execution (however, with the same sort of data flow analysis that dbr
does, we could have figured out before that we don't need to
conditionalize this insn.)
what to do with COND_EXEC. */
if (RTX_FRAME_RELATED_P (insn))
{
- /* If this is the delay slot insn of an anulled branch,
- dwarf2out.cc:scan_trace understands the anulling semantics
+ /* If this is the delay slot insn of an annulled branch,
+ dwarf2out.cc:scan_trace understands the annulling semantics
without the COND_EXEC. */
gcc_assert (annulled);
rtx note = alloc_reg_note (REG_FRAME_RELATED_EXPR, pat,
return false;
}
-/* ??? Should we define TARGET_REGISTER_PRIORITY? We might perfer to
+/* ??? Should we define TARGET_REGISTER_PRIORITY? We might prefer to
use q registers, because some insn are shorter with them. OTOH we
already have separate alternatives for this purpose, and other
insns don't mind, so maybe we should rather prefer the other
one OR instruction:
OR rA, rB, mask -> OR rA,rB,mask1/BSET_S rA,mask2
- 3. otherwise an OR with limm will be emmitted. */
+ 3. otherwise an OR with limm will be emitted. */
void
arc_split_ior (rtx *operands)
#define TARGET_CPU_CPP_BUILTINS() arc_cpu_cpp_builtins (pfile)
/* Macros enabled by specific command line option. FIXME: to be
- deprecatd. */
+ deprecated. */
#define CPP_SPEC "\
%{msimd:-D__Xsimd} %{mno-mpy:-D__Xno_mpy} %{mswap:-D__Xswap} \
%{mmin-max:-D__Xmin_max} %{mEA:-D__Xea} \
/* Should we add padding before a return insn to avoid mispredict? */
#define TARGET_PAD_RETURN (TARGET_ARC700 && !optimize_size)
-/* For an anulled-true delay slot insn for a delayed branch, should we only
+/* For an annulled-true delay slot insn for a delayed branch, should we only
use conditional execution? */
#define TARGET_AT_DBR_CONDEXEC (!TARGET_ARC700 && !TARGET_V2)
These extra instructions - and the second comparison - will also be
an extra cost if the first comparison would have been decisive.
So get an average saving, with a probability of the first branch
- beging decisive of p0, we want:
+ being decisive of p0, we want:
p0 * (branch_cost - 4) > (1 - p0) * 5
??? We don't get to see that probability to evaluate, so we can
only wildly guess that it might be 50%. */
because that would lead to infinite recursion as the attribute test
needs to recognize the insn. So, instead we have a clause for
the pattern condition of all sfunc patterns which is only relevant for
- the predicated varaint. */
+ the predicated variant. */
#define SFUNC_CHECK_PREDICABLE \
(GET_CODE (PATTERN (insn)) != COND_EXEC || !flag_pic || !TARGET_MEDIUM_CALLS)
;; Delay slot definition for ARCompact ISA
;; ??? FIXME:
-;; When outputting an annul-true insn elegible for cond-exec
+;; When outputting an annul-true insn eligible for cond-exec
;; in a cbranch delay slot, unless optimizing for size, we use cond-exec
;; for ARC600; we could also use this for ARC700 if the branch can't be
;; unaligned and is at least somewhat likely (add parameter for this).
})
;; ??? Could add a peephole to generate compare with swapped operands and
-;; modifed cc user if second, but not first operand is a compact register.
+;; modified cc user if second, but not first operand is a compact register.
(define_insn "cmpsi_cc_insn_mixed"
[(set (reg:CC CC_REG)
(compare:CC (match_operand:SI 0 "register_operand" "q, q, h, c, c, q,c")
; are three reasons why we need to consider branches to be length 6:
; - annull-false delay slot insns are implemented using conditional execution,
; thus preventing short insn formation where used.
-; - for ARC600: annull-true delay slot isnns are implemented where possile
+; - for ARC600: annull-true delay slot isnns are implemented where possible
; using conditional execution, preventing short insn formation where used.
; - for ARC700: likely or somewhat likely taken branches are made long and
; unaligned if possible to avoid branch penalty.
;; Comment in final.cc (insn_current_reference_address) says
;; forward branch addresses are calculated from the next insn after branch
;; and for backward branches, it is calculated from the branch insn start.
- ;; The shortening logic here is tuned to accomodate this behavior
+ ;; The shortening logic here is tuned to accommodate this behavior
;; ??? This should be grokked by the ccfsm machinery.
(define_insn "cbranchsi4_scratch"
[(set (pc)
(match_operand:SI 3 "const_int_operand" "")))]
"TARGET_NPS_BITOPS")
-; We need a sanity check in the instuction predicate because combine
+; We need a sanity check in the instruction predicate because combine
; will throw any old rubbish at us and see what sticks.
(define_insn "*extzv_i"
[(set (match_operand:SI 0 "register_operand" "=Rrq")
Target Ignore Undocumented
Does nothing. Preserved for backward compatibility.
-; We use an explict definition for the negative form because that is the
+; We use an explicit definition for the negative form because that is the
; actually interesting option, and we want that to have its own comment.
mvolatile-cache
Target RejectNegative Mask(VOLATILE_CACHE_SET)
(define_bypass 1 "compare_700" "branch_700,core_insn,data_store,data_load")
-; we could shedule the cmove immediately after the compare, but then
+; we could schedule the cmove immediately after the compare, but then
; the cmove would have higher latency... so just keep the cmove apart
; from the compare.
(define_bypass 2 "compare_700" "cmove")
#undef TARGET_ASM_FILE_END
#define TARGET_ASM_FILE_END arc_file_end
-/* If no specs file is enforced, default to nosys libarary. */
+/* If no specs file is enforced, default to nosys library. */
#undef LINK_GCC_C_SEQUENCE_SPEC
#define LINK_GCC_C_SEQUENCE_SPEC \
"--start-group %G %{!specs=*:%{!nolibc:-lc -lnosys}} --end-group"
Because of the Newton-raphson iteration step, an error in the seed at X
is amplified by X. Therefore, we don't want a Tchebycheff polynom
or a polynom that is close to optimal according to the maximum norm
- on the errro of the seed value; we want one that is close to optimal
+ on the error of the seed value; we want one that is close to optimal
according to the maximum norm on the error of the result, i.e. we
- want the maxima of the polynom to increase linearily.
+ want the maxima of the polynom to increase linearly.
Given an interval [X0,X2) over which to approximate,
with X1 := (X0+X2)/2, D := X1-X0, F := 1/D, and S := D/X1 we have,
like for Tchebycheff polynoms:
Because of the Newton-raphson iteration step, an error in the seed at X
is amplified by X. Therefore, we don't want a Tchebycheff polynom
or a polynom that is close to optimal according to the maximum norm
- on the errro of the seed value; we want one that is close to optimal
+ on the error of the seed value; we want one that is close to optimal
according to the maximum norm on the error of the result, i.e. we
- want the maxima of the polynom to increase linearily.
+ want the maxima of the polynom to increase linearly.
Given an interval [X0,X2) over which to approximate,
with X1 := (X0+X2)/2, D := X1-X0, F := 1/D, and S := D/X1 we have,
like for Tchebycheff polynoms:
projects / thirdparty / gcc.git / commitdiff
