drm/amdgpu/mes12_1: fix the failure access to MID1 registers

Correct the mid die id and mid1 register relative offset
for mes fw to access to mid1 registers.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
index ca8cacd34573608544f7be6b24330846afd1d022..5dcc2c32644aec78ebca754ac666ad23484e896f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
@@ -494,16 +494,12 @@ static int mes_v12_1_query_sched_status(struct amdgpu_mes *mes,
 }
 static uint32_t mes_v12_1_get_xcc_from_reg(uint32_t reg_offset)
 {
-       /* Check xcc reg offset range */
-       uint32_t xcc = (reg_offset & XCC_MID_MASK) ? 4 : 0;
-       /* Each XCC has two register ranges.
-        * These are represented in reg_offset[17:16]
-        */
-       return ((reg_offset >> 16) & 0x3) + xcc;
+       return ((reg_offset >> 16) & 0x7);
 }
 
 static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id,
-                                struct RRMT_OPTION *rrmt_opt)
+                              struct RRMT_OPTION *rrmt_opt,
+                              uint32_t *out_reg)
 {
        uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg);
 
@@ -513,7 +509,11 @@ static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id,
                         MES_RRMT_MODE_LOCAL_XCD : MES_RRMT_MODE_REMOTE_XCD;
        } else {
                rrmt_opt->mode = MES_RRMT_MODE_REMOTE_MID;
+               if (soc_v1_0_mid1_reg_range(reg))
+                       rrmt_opt->mid_die_id = 1;
        }
+
+       *out_reg = soc_v1_0_normalize_reg_offset(reg);
 }
 
 static int mes_v12_1_misc_op(struct amdgpu_mes *mes,
@@ -537,65 +537,44 @@ static int mes_v12_1_misc_op(struct amdgpu_mes *mes,
        switch (input->op) {
        case MES_MISC_OP_READ_REG:
                misc_pkt.opcode = MESAPI_MISC__READ_REG;
-               misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
                misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
                mes_v12_1_get_rrmt(input->read_reg.reg_offset,
                                   GET_INST(GC, input->xcc_id),
-                                  &misc_pkt.read_reg.rrmt_opt);
-               if (misc_pkt.read_reg.rrmt_opt.mode != MES_RRMT_MODE_REMOTE_MID) {
-                       misc_pkt.read_reg.reg_offset =
-                               soc_v1_0_normalize_xcc_reg_offset(misc_pkt.read_reg.reg_offset);
-               }
+                                  &misc_pkt.read_reg.rrmt_opt,
+                                  &misc_pkt.read_reg.reg_offset);
                break;
        case MES_MISC_OP_WRITE_REG:
                misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
-               misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
                misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
                mes_v12_1_get_rrmt(input->write_reg.reg_offset,
                                   GET_INST(GC, input->xcc_id),
-                                  &misc_pkt.write_reg.rrmt_opt);
-               if (misc_pkt.write_reg.rrmt_opt.mode != MES_RRMT_MODE_REMOTE_MID) {
-                       misc_pkt.write_reg.reg_offset =
-                               soc_v1_0_normalize_xcc_reg_offset(misc_pkt.write_reg.reg_offset);
-               }
+                                  &misc_pkt.write_reg.rrmt_opt,
+                                  &misc_pkt.write_reg.reg_offset);
                break;
        case MES_MISC_OP_WRM_REG_WAIT:
                misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
                misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
                misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
                misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
-               misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
                misc_pkt.wait_reg_mem.reg_offset2 = 0;
                mes_v12_1_get_rrmt(input->wrm_reg.reg0,
                                   GET_INST(GC, input->xcc_id),
-                                  &misc_pkt.wait_reg_mem.rrmt_opt1);
-               if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) {
-                       misc_pkt.wait_reg_mem.reg_offset1 =
-                               soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset1);
-               }
+                                  &misc_pkt.wait_reg_mem.rrmt_opt1,
+                                  &misc_pkt.wait_reg_mem.reg_offset1);
                break;
        case MES_MISC_OP_WRM_REG_WR_WAIT:
                misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
                misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
                misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
                misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
-               misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
-               misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
                mes_v12_1_get_rrmt(input->wrm_reg.reg0,
                                   GET_INST(GC, input->xcc_id),
-                                  &misc_pkt.wait_reg_mem.rrmt_opt1);
+                                  &misc_pkt.wait_reg_mem.rrmt_opt1,
+                                  &misc_pkt.wait_reg_mem.reg_offset1);
                mes_v12_1_get_rrmt(input->wrm_reg.reg1,
                                   GET_INST(GC, input->xcc_id),
-                                  &misc_pkt.wait_reg_mem.rrmt_opt2);
-
-               if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) {
-                       misc_pkt.wait_reg_mem.reg_offset1 =
-                               soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset1);
-               }
-               if (misc_pkt.wait_reg_mem.rrmt_opt2.mode != MES_RRMT_MODE_REMOTE_MID) {
-                       misc_pkt.wait_reg_mem.reg_offset2 =
-                               soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset2);
-               }
+                                  &misc_pkt.wait_reg_mem.rrmt_opt2,
+                                  &misc_pkt.wait_reg_mem.reg_offset2);
                break;
        case MES_MISC_OP_SET_SHADER_DEBUGGER:
                pipe = AMDGPU_MES_SCHED_PIPE;

diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
index 0c7759b82fa63c4cf99a6f467c33fa865707f909..37552c91a8781dda86a8947fe51800dfe7ea27d7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
@@ -41,6 +41,11 @@
 #define NORMALIZE_XCC_REG_OFFSET(offset) \
        (offset & 0xFFFF)
 
+#define MID1_REG_RANGE_0_LOW  0x40000
+#define MID1_REG_RANGE_0_HIGH 0x80000
+#define NORMALIZE_MID_REG_OFFSET(offset) \
+               (offset & 0x3FFFF)
+
 /* Initialized doorbells for amdgpu including multimedia
  * KFD can use all the rest in 2M doorbell bar */
 static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev)
@@ -870,3 +875,31 @@ uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg)
        else
                return reg;
 }
+
+bool soc_v1_0_mid1_reg_range(uint32_t reg)
+{
+       uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg);
+
+       if (soc_v1_0_normalize_xcc_reg_range(normalized_reg))
+               return false;
+
+       if ((reg >= MID1_REG_RANGE_0_LOW) && (reg < MID1_REG_RANGE_0_HIGH))
+               return true;
+       else
+               return false;
+}
+
+uint32_t soc_v1_0_normalize_reg_offset(uint32_t reg)
+{
+       uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg);
+
+       if (soc_v1_0_normalize_xcc_reg_range(normalized_reg))
+               return soc_v1_0_normalize_xcc_reg_offset(reg);
+
+       /* check if the reg offset is inside MID1. */
+       if (soc_v1_0_mid1_reg_range(reg))
+               return NORMALIZE_MID_REG_OFFSET(reg);
+
+       return reg;
+}
+

diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h
index 146996101aa07eecfc0d48aa4338e4917c477226..16c220fcc4e92a8f03ac05f9cbe1681b682ad716 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h
@@ -31,7 +31,9 @@ void soc_v1_0_grbm_select(struct amdgpu_device *adev,
                          int xcc_id);
 int soc_v1_0_init_soc_config(struct amdgpu_device *adev);
 bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg);
+bool soc_v1_0_mid1_reg_range(uint32_t reg);
 uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg);
+uint32_t soc_v1_0_normalize_reg_offset(uint32_t reg);
 u64 soc_v1_0_encode_ext_smn_addressing(int ext_id);
 
 #endif