mmc: sdhci-esdhc-imx: optimize clock loopback selection with dummy pad support

For legacy platforms without dummy pad:
When clock <= 100MHz: Set ESDHC_MIX_CTRL_FBCLK_SEL to 0 (external clock
pad loopback) for better bus clock proximity.
When clock > 100MHz: Set ESDHC_MIX_CTRL_FBCLK_SEL to 1 (internal clock
loopback) to avoid signal reflection noise at high frequency.

For i.MX94/95 with dummy pad support:
Keep ESDHC_MIX_CTRL_FBCLK_SEL at 0 for all speed mode. Hardware
automatically substitutes clock pad loopback with dummy pad loopback
when available, eliminating signal reflections while preserving better
bus clock proximity.

Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20250521025502.112030-2-ziniu.wang_1@nxp.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 1b51137803c934e9e20121f4465b62ae66761310..e795e431e16e9fe8c2f415616b8e038fefc07a0d 100644 (file)
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -212,6 +212,9 @@
 /* The IP does not have GPIO CD wake capabilities */
 #define ESDHC_FLAG_SKIP_CD_WAKE                BIT(18)
 
+/* the controller has dummy pad for clock loopback */
+#define ESDHC_FLAG_DUMMY_PAD           BIT(19)
+
 #define ESDHC_AUTO_TUNING_WINDOW       3
 
 enum wp_types {
@@ -348,6 +351,15 @@ static struct esdhc_soc_data usdhc_imx8mm_data = {
        .quirks = SDHCI_QUIRK_NO_LED,
 };
 
+static struct esdhc_soc_data usdhc_imx95_data = {
+       .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
+                       | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+                       | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
+                       | ESDHC_FLAG_STATE_LOST_IN_LPMODE
+                       | ESDHC_FLAG_DUMMY_PAD,
+       .quirks = SDHCI_QUIRK_NO_LED,
+};
+
 struct pltfm_imx_data {
        u32 scratchpad;
        struct pinctrl *pinctrl;
@@ -392,6 +404,8 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
        { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
        { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
        { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
+       { .compatible = "fsl,imx94-usdhc", .data = &usdhc_imx95_data, },
+       { .compatible = "fsl,imx95-usdhc", .data = &usdhc_imx95_data, },
        { .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, },
        { .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
        { /* sentinel */ }
@@ -1424,9 +1438,10 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
                break;
        }
 
-       if (timing == MMC_TIMING_UHS_SDR104 ||
-           timing == MMC_TIMING_MMC_HS200 ||
-           timing == MMC_TIMING_MMC_HS400)
+       if (!(imx_data->socdata->flags & ESDHC_FLAG_DUMMY_PAD) &&
+           (timing == MMC_TIMING_UHS_SDR104 ||
+            timing == MMC_TIMING_MMC_HS200 ||
+            timing == MMC_TIMING_MMC_HS400))
                m |= ESDHC_MIX_CTRL_FBCLK_SEL;
        else
                m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
@@ -1678,7 +1693,9 @@ static void sdhc_esdhc_tuning_restore(struct sdhci_host *host)
                writel(reg, host->ioaddr + ESDHC_TUNING_CTRL);
 
                reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
-               reg |= ESDHC_MIX_CTRL_SMPCLK_SEL | ESDHC_MIX_CTRL_FBCLK_SEL;
+               reg |= ESDHC_MIX_CTRL_SMPCLK_SEL;
+               if (!(imx_data->socdata->flags & ESDHC_FLAG_DUMMY_PAD))
+                       reg |= ESDHC_MIX_CTRL_FBCLK_SEL;
                writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 
                writel(FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK,