]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
accel/amdxdna: Update firmware version check for latest firmware
authorLizhi Hou <lizhi.hou@amd.com>
Fri, 19 Dec 2025 01:43:56 +0000 (17:43 -0800)
committerLizhi Hou <lizhi.hou@amd.com>
Thu, 8 Jan 2026 17:48:43 +0000 (09:48 -0800)
The latest firmware increases the major version number. Update
aie2_check_protocol() to accept and support the new firmware version.

Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
Link: https://patch.msgid.link/20251219014356.2234241-2-lizhi.hou@amd.com
drivers/accel/amdxdna/aie2_pci.c
drivers/accel/amdxdna/aie2_pci.h
drivers/accel/amdxdna/npu1_regs.c
drivers/accel/amdxdna/npu4_regs.c
drivers/accel/amdxdna/npu5_regs.c
drivers/accel/amdxdna/npu6_regs.c

index 81a8e4137bfd093c2c1733979e44a39dd2a361e5..181fdbc10daec325bd1e924e724e2d38a65cd4d4 100644 (file)
@@ -56,41 +56,23 @@ struct mgmt_mbox_chann_info {
 static int aie2_check_protocol(struct amdxdna_dev_hdl *ndev, u32 fw_major, u32 fw_minor)
 {
        const struct aie2_fw_feature_tbl *feature;
-       struct amdxdna_dev *xdna = ndev->xdna;
-
-       /*
-        * The driver supported mailbox behavior is defined by
-        * ndev->priv->protocol_major and protocol_minor.
-        *
-        * When protocol_major and fw_major are different, it means driver
-        * and firmware are incompatible.
-        */
-       if (ndev->priv->protocol_major != fw_major) {
-               XDNA_ERR(xdna, "Incompatible firmware protocol major %d minor %d",
-                        fw_major, fw_minor);
-               return -EINVAL;
-       }
+       bool found = false;
 
-       /*
-        * When protocol_minor is greater then fw_minor, that means driver
-        * relies on operation the installed firmware does not support.
-        */
-       if (ndev->priv->protocol_minor > fw_minor) {
-               XDNA_ERR(xdna, "Firmware minor version smaller than supported");
-               return -EINVAL;
-       }
-
-       for (feature = ndev->priv->fw_feature_tbl; feature && feature->min_minor;
-            feature++) {
+       for (feature = ndev->priv->fw_feature_tbl; feature->major; feature++) {
+               if (feature->major != fw_major)
+                       continue;
                if (fw_minor < feature->min_minor)
                        continue;
                if (feature->max_minor > 0 && fw_minor > feature->max_minor)
                        continue;
 
-               set_bit(feature->feature, &ndev->feature_mask);
+               ndev->feature_mask |= feature->features;
+
+               /* firmware version matches one of the driver support entry */
+               found = true;
        }
 
-       return 0;
+       return found ? 0 : -EOPNOTSUPP;
 }
 
 static void aie2_dump_chann_info_debug(struct amdxdna_dev_hdl *ndev)
index e1745f07b268ed5ec515ec234df1e5648690e41c..b20a3661078cc1b27547501ae363568358beb651 100644 (file)
@@ -237,7 +237,8 @@ enum aie2_fw_feature {
 };
 
 struct aie2_fw_feature_tbl {
-       enum aie2_fw_feature feature;
+       u64 features;
+       u32 major;
        u32 max_minor;
        u32 min_minor;
 };
@@ -246,8 +247,6 @@ struct aie2_fw_feature_tbl {
 
 struct amdxdna_dev_priv {
        const char                      *fw_path;
-       u64                             protocol_major;
-       u64                             protocol_minor;
        const struct rt_config          *rt_config;
        const struct dpm_clk_freq       *dpm_clk_tbl;
        const struct aie2_fw_feature_tbl *fw_feature_tbl;
index ebc6e28022971d8db9903c3656dd1d29b8029edb..6f36a27b5a02d88236eeb0407840d5af3314d0f5 100644 (file)
@@ -6,6 +6,7 @@
 #include <drm/amdxdna_accel.h>
 #include <drm/drm_device.h>
 #include <drm/gpu_scheduler.h>
+#include <linux/bits.h>
 #include <linux/sizes.h>
 
 #include "aie2_pci.h"
@@ -65,14 +66,13 @@ const struct dpm_clk_freq npu1_dpm_clk_table[] = {
 };
 
 static const struct aie2_fw_feature_tbl npu1_fw_feature_table[] = {
-       { .feature = AIE2_NPU_COMMAND, .min_minor = 8 },
+       { .major = 5, .min_minor = 7 },
+       { .features = BIT_U64(AIE2_NPU_COMMAND), .min_minor = 8 },
        { 0 }
 };
 
 static const struct amdxdna_dev_priv npu1_dev_priv = {
        .fw_path        = "amdnpu/1502_00/npu.sbin",
-       .protocol_major = 0x5,
-       .protocol_minor = 0x7,
        .rt_config      = npu1_default_rt_cfg,
        .dpm_clk_tbl    = npu1_dpm_clk_table,
        .fw_feature_tbl = npu1_fw_feature_table,
index a62234fd266d47efacca9a97532226d9e121528d..a8d6f76dde5f9db21d966616cc23b68548749fd0 100644 (file)
@@ -6,6 +6,7 @@
 #include <drm/amdxdna_accel.h>
 #include <drm/drm_device.h>
 #include <drm/gpu_scheduler.h>
+#include <linux/bits.h>
 #include <linux/sizes.h>
 
 #include "aie2_pci.h"
@@ -88,16 +89,16 @@ const struct dpm_clk_freq npu4_dpm_clk_table[] = {
 };
 
 const struct aie2_fw_feature_tbl npu4_fw_feature_table[] = {
-       { .feature = AIE2_NPU_COMMAND, .min_minor = 15 },
-       { .feature = AIE2_PREEMPT, .min_minor = 12 },
-       { .feature = AIE2_TEMPORAL_ONLY, .min_minor = 12 },
+       { .major = 6, .min_minor = 12 },
+       { .features = BIT_U64(AIE2_NPU_COMMAND), .major = 6, .min_minor = 15 },
+       { .features = BIT_U64(AIE2_PREEMPT), .major = 6, .min_minor = 12 },
+       { .features = BIT_U64(AIE2_TEMPORAL_ONLY), .major = 6, .min_minor = 12 },
+       { .features = GENMASK_ULL(AIE2_TEMPORAL_ONLY, AIE2_NPU_COMMAND), .major = 7 },
        { 0 }
 };
 
 static const struct amdxdna_dev_priv npu4_dev_priv = {
        .fw_path        = "amdnpu/17f0_10/npu.sbin",
-       .protocol_major = 0x6,
-       .protocol_minor = 12,
        .rt_config      = npu4_default_rt_cfg,
        .dpm_clk_tbl    = npu4_dpm_clk_table,
        .fw_feature_tbl = npu4_fw_feature_table,
index 131080652ef08bd3d85cce3524178f63c8c6b275..c0a35cfd886cc44204f1c64c33953c263a45103a 100644 (file)
@@ -64,8 +64,6 @@
 
 static const struct amdxdna_dev_priv npu5_dev_priv = {
        .fw_path        = "amdnpu/17f0_11/npu.sbin",
-       .protocol_major = 0x6,
-       .protocol_minor = 12,
        .rt_config      = npu4_default_rt_cfg,
        .dpm_clk_tbl    = npu4_dpm_clk_table,
        .fw_feature_tbl = npu4_fw_feature_table,
index 1f71285655b2ae83f4e1d9a572cd6b8d9244328f..1fb07df9918601535d11e6c72fdb87d3e343b452 100644 (file)
@@ -64,8 +64,6 @@
 
 static const struct amdxdna_dev_priv npu6_dev_priv = {
        .fw_path        = "amdnpu/17f0_10/npu.sbin",
-       .protocol_major = 0x6,
-       .protocol_minor = 12,
        .rt_config      = npu4_default_rt_cfg,
        .dpm_clk_tbl    = npu4_dpm_clk_table,
        .fw_feature_tbl = npu4_fw_feature_table,