arm64: Document SVE constraints on new hwcaps

Two of the SVE hwcaps added for the SVE features in the 2025 dpISA did
not explicitly call out their dependency on SVE in the ABI documentation.
Do so.

While we're here reorder the SVE and fature specific ID registers for
HWCAP3_SVE_LUT6 which did have the SVE dependency but listed it second
unlike the other SVE specific ID registers.

Fixes: abca5e69ab62 ("arm64/cpufeature: Define hwcaps for 2025 dpISA features")
Reported-by: Will Deacon <will@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst
index 07ff9ea1d6055bc435b11b3c5bf18176670cba1e..f60ca5612daa439b498166a1a7d6b889b3b1f707 100644 (file)
--- a/Documentation/arch/arm64/elf_hwcaps.rst
+++ b/Documentation/arch/arm64/elf_hwcaps.rst
@@ -452,10 +452,12 @@ HWCAP3_LS64
     memory location, otherwise fallback to the non-atomic alternatives.
 
 HWCAP3_SVE_B16MM
-    Functionality implied by ID_AA64ZFR0_EL1.B16B16 == 0b0011
+    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
+    ID_AA64ZFR0_EL1.B16B16 == 0b0011
 
 HWCAP3_SVE2P3
-    Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0100
+    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
+    ID_AA64ZFR0_EL1.SVEver == 0b0100
 
 HWCAP3_SME_LUT6
     Functionality implied by ID_AA64SMFR0_EL1.LUT6 == 0b1
@@ -473,8 +475,9 @@ HWCAP3_F16F32MM
     Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0011
 
 HWCAP3_SVE_LUT6
-    Functionality implied by ID_AA64ISAR2_EL1.LUT == 0b0010 and
-    ID_AA64PFR0_EL1.SVE == 0b0001.
+    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
+    ID_AA64ISAR2_EL1.LUT == 0b0010.
+
 
 4. Unused AT_HWCAP bits
 -----------------------