arm64: dts: cavium: Drop thunder2

The Cavium thunder2 DT support is incomplete. It consists of 4 cores
(out of 128) and only a serial port. The thunder2 specific drivers in
the kernel don't have DT support either. The few remaining users of
this platform likely use ACPI.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251216180202.2794695-2-robh@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile
index c178f7e06e18e016d0ab6ee034862e230af043ad..8a1854380993e82de23226387e936749326522c7 100644 (file)
--- a/arch/arm64/boot/dts/cavium/Makefile
+++ b/arch/arm64/boot/dts/cavium/Makefile
@@ -1,3 +1,2 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
-dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb

diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts
deleted file mode 100644 (file)
index 89fc410..0000000
--- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * dts file for Cavium ThunderX2 CN99XX Evaluation Platform
- *
- * Copyright (c) 2017 Cavium Inc.
- * Copyright (c) 2013-2016 Broadcom
- */
-
-/dts-v1/;
-
-#include "thunder2-99xx.dtsi"
-
-/ {
-       model = "Cavium ThunderX2 CN99XX";
-       compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
-
-       memory@80000000 {
-               device_type = "memory";
-               reg = <0x00000000 0x80000000 0x0 0x80000000>,  /* 2G @ 2G  */
-                     <0x00000008 0x80000000 0x0 0x80000000>;  /* 2G @ 34G */
-       };
-
-       aliases {
-               serial0 = &uart0;
-       };
-
-       chosen {
-               stdout-path = "serial0:115200n8";
-       };
-};

diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
deleted file mode 100644 (file)
index 966fb57..0000000
--- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
+++ /dev/null
@@ -1,144 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * dtsi file for Cavium ThunderX2 CN99XX processor
- *
- * Copyright (c) 2017 Cavium Inc.
- * Copyright (c) 2013-2016 Broadcom
- * Author: Zi Shen Lim <zlim@broadcom.com>
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-       model = "Cavium ThunderX2 CN99XX";
-       compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
-       interrupt-parent = <&gic>;
-       #address-cells = <2>;
-       #size-cells = <2>;
-
-       /* just 4 cpus now, 128 needed in full config */
-       cpus {
-               #address-cells = <0x2>;
-               #size-cells = <0x0>;
-
-               cpu@0 {
-                       device_type = "cpu";
-                       compatible = "cavium,thunder2", "brcm,vulcan";
-                       reg = <0x0 0x0>;
-                       enable-method = "psci";
-               };
-
-               cpu@1 {
-                       device_type = "cpu";
-                       compatible = "cavium,thunder2", "brcm,vulcan";
-                       reg = <0x0 0x1>;
-                       enable-method = "psci";
-               };
-
-               cpu@2 {
-                       device_type = "cpu";
-                       compatible = "cavium,thunder2", "brcm,vulcan";
-                       reg = <0x0 0x2>;
-                       enable-method = "psci";
-               };
-
-               cpu@3 {
-                       device_type = "cpu";
-                       compatible = "cavium,thunder2", "brcm,vulcan";
-                       reg = <0x0 0x3>;
-                       enable-method = "psci";
-               };
-       };
-
-       psci {
-               compatible = "arm,psci-0.2";
-               method = "smc";
-       };
-
-       gic: interrupt-controller@4000080000 {
-               compatible = "arm,gic-v3";
-               #interrupt-cells = <3>;
-               #address-cells = <2>;
-               #size-cells = <2>;
-               ranges;
-               interrupt-controller;
-               #redistributor-regions = <1>;
-               reg = <0x04 0x00080000 0x0 0x20000>,    /* GICD */
-                     <0x04 0x01000000 0x0 0x1000000>;  /* GICR */
-               interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-
-               gicits: msi-controller@4000100000 {
-                       compatible = "arm,gic-v3-its";
-                       msi-controller;
-                       reg = <0x04 0x00100000 0x0 0x20000>;    /* GIC ITS */
-               };
-       };
-
-       timer {
-               compatible = "arm,armv8-timer";
-               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
-       };
-
-       pmu {
-               compatible = "brcm,vulcan-pmu";
-               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */
-       };
-
-       clk125mhz: uart_clk125mhz {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <125000000>;
-               clock-output-names = "clk125mhz";
-       };
-
-       pcie@30000000 {
-               compatible = "pci-host-ecam-generic";
-               device_type = "pci";
-               #interrupt-cells = <1>;
-               #address-cells = <3>;
-               #size-cells = <2>;
-
-               /* ECAM at 0x3000_0000 - 0x4000_0000 */
-               reg = <0x0 0x30000000  0x0 0x10000000>;
-
-               /*
-                * PCI ranges:
-                *   IO         no supported
-                *   MEM        0x4000_0000 - 0x6000_0000
-                *   MEM64 pref 0x40_0000_0000 - 0x60_0000_0000
-                */
-               ranges =
-                 <0x02000000    0 0x40000000    0 0x40000000    0 0x20000000
-                  0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>;
-               bus-range = <0 0xff>;
-               interrupt-map-mask = <0 0 0 7>;
-               interrupt-map =
-                     /* addr  pin  ic   icaddr  icintr */
-                       <0 0 0  1  &gic   0 0    GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
-                        0 0 0  2  &gic   0 0    GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
-                        0 0 0  3  &gic   0 0    GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
-                        0 0 0  4  &gic   0 0    GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-               msi-parent = <&gicits>;
-               dma-coherent;
-       };
-
-       soc {
-               compatible = "simple-bus";
-               #address-cells = <2>;
-               #size-cells = <2>;
-               ranges;
-
-               uart0: serial@402020000 {
-                       compatible = "arm,pl011", "arm,primecell";
-                       reg = <0x04 0x02020000 0x0 0x1000>;
-                       interrupt-parent = <&gic>;
-                       interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clk125mhz>, <&clk125mhz>;
-                       clock-names = "uartclk", "apb_pclk";
-               };
-       };
-
-};