[PR83370][AARCH64]Use tighter register constraint for sibcall patterns.

gcc/

	backport from mainline
	2018-02-01  Renlin Li  <renlin.li@arm.com>

	PR target/83370
	* config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle
	TAILCALL_ADDR_REGS.
	(aarch64_register_move_cost): Likewise.
	* config/aarch64/aarch64.h (reg_class): Rename CALLER_SAVE_REGS to
	TAILCALL_ADDR_REGS.
	(REG_CLASS_NAMES): Likewise.
	(REG_CLASS_CONTENTS): Rename CALLER_SAVE_REGS to
	TAILCALL_ADDR_REGS. Remove IP registers.
	* config/aarch64/aarch64.md (Ucs): Update register constraint.

gcc/testsuite/

	backport from mainline
	2018-02-01  Richard Sandiford  <richard.sandiford@linaro.org>

	PR target/83370
	* gcc.target/aarch64/pr83370.c: New.

From-SVN: r257315

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b2e4e8180e3a5fcb9342032c1a8d368acd47fa17..e6061b95a89b3790e28a5802ca9d616c78260014 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,19 @@
+2018-02-01  Renlin Li  <renlin.li@arm.com>
+
+       Backport from mainline
+       2018-02-01  Renlin Li  <renlin.li@arm.com>
+
+       PR target/83370
+       * config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle
+       TAILCALL_ADDR_REGS.
+       (aarch64_register_move_cost): Likewise.
+       * config/aarch64/aarch64.h (reg_class): Rename CALLER_SAVE_REGS to
+       TAILCALL_ADDR_REGS.
+       (REG_CLASS_NAMES): Likewise.
+       (REG_CLASS_CONTENTS): Rename CALLER_SAVE_REGS to
+       TAILCALL_ADDR_REGS. Remove IP registers.
+       * config/aarch64/aarch64.md (Ucs): Update register constraint.
+
 2018-02-01  Bin Cheng  <bin.cheng@arm.com>
 
        Backport from mainline

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index b2f0958abab4c928813c0c882692a29c0b8b130d..cce8cf89b3c0b536c38b2d5235d6c348a4404234 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -5337,7 +5337,7 @@ aarch64_class_max_nregs (reg_class_t regclass, machine_mode mode)
 {
   switch (regclass)
     {
-    case CALLER_SAVE_REGS:
+    case TAILCALL_ADDR_REGS:
     case POINTER_REGS:
     case GENERAL_REGS:
     case ALL_REGS:
@@ -7383,10 +7383,10 @@ aarch64_register_move_cost (machine_mode mode,
     = aarch64_tune_params.regmove_cost;
 
   /* Caller save and pointer regs are equivalent to GENERAL_REGS.  */
-  if (to == CALLER_SAVE_REGS || to == POINTER_REGS)
+  if (to == TAILCALL_ADDR_REGS || to == POINTER_REGS)
     to = GENERAL_REGS;
 
-  if (from == CALLER_SAVE_REGS || from == POINTER_REGS)
+  if (from == TAILCALL_ADDR_REGS || from == POINTER_REGS)
     from = GENERAL_REGS;
 
   /* Moving between GPR and stack cost is the same as GP2GP.  */

diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 24defeb13282675712457ca637ca11c2bc736eab..a8c0fac340aaca553dc3cdfccf338a100cb38765 100644 (file)
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -420,7 +420,7 @@ extern unsigned aarch64_architecture_version;
 enum reg_class
 {
   NO_REGS,
-  CALLER_SAVE_REGS,
+  TAILCALL_ADDR_REGS,
   GENERAL_REGS,
   STACK_REG,
   POINTER_REGS,
@@ -435,7 +435,7 @@ enum reg_class
 #define REG_CLASS_NAMES                                \
 {                                              \
   "NO_REGS",                                   \
-  "CALLER_SAVE_REGS",                          \
+  "TAILCALL_ADDR_REGS",                                \
   "GENERAL_REGS",                              \
   "STACK_REG",                                 \
   "POINTER_REGS",                              \
@@ -447,7 +447,7 @@ enum reg_class
 #define REG_CLASS_CONTENTS                                             \
 {                                                                      \
   { 0x00000000, 0x00000000, 0x00000000 },      /* NO_REGS */           \
-  { 0x0007ffff, 0x00000000, 0x00000000 },      /* CALLER_SAVE_REGS */  \
+  { 0x0004ffff, 0x00000000, 0x00000000 },      /* TAILCALL_ADDR_REGS */\
   { 0x7fffffff, 0x00000000, 0x00000003 },      /* GENERAL_REGS */      \
   { 0x80000000, 0x00000000, 0x00000000 },      /* STACK_REG */         \
   { 0xffffffff, 0x00000000, 0x00000003 },      /* POINTER_REGS */      \

diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index d64a7ebe36fcc7e022441392d81d07cec07fd08b..8c279cb62b335f68540c198a17e5c308a88632bc 100644 (file)
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -21,8 +21,8 @@
 (define_register_constraint "k" "STACK_REG"
   "@internal The stack register.")
 
-(define_register_constraint "Ucs" "CALLER_SAVE_REGS"
-  "@internal The caller save registers.")
+(define_register_constraint "Ucs" "TAILCALL_ADDR_REGS"
+  "@internal Registers suitable for an indirect tail call")
 
 (define_register_constraint "w" "FP_REGS"
   "Floating point and SIMD vector registers.")

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9e4fffebe700bd40b4a92db177f78231bc8f1de7..7b73816e9ed7b3f0adc0dd8499ab45bcc5610222 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2018-02-01  Renlin Li  <renlin.li@arm.com>
+
+       Backport from mainline
+       2018-02-01  Richard Sandiford  <richard.sandiford@linaro.org>
+
+       PR target/83370
+       * gcc.target/aarch64/pr83370.c: New.
+
 2018-02-01  Bin Cheng  <bin.cheng@arm.com>
 
        Backport from mainline

diff --git a/gcc/testsuite/gcc.target/aarch64/pr83370.c b/gcc/testsuite/gcc.target/aarch64/pr83370.c
new file mode 100644 (file)
index 0000000..001373c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr83370.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+typedef void (*fun) (void);
+
+void
+f (fun x1)
+{
+  register fun x2 asm ("x16");
+  int arr[5000];
+  int *volatile ptr = arr;
+  asm ("mov %0, %1" : "=r" (x2) : "r" (x1));
+  x2 ();
+}
+
+void g (void) {}
+
+int
+main (void)
+{
+  f (g);
+}