ARM: dts: aspeed: anacapa: Correct SGPIO names for monitoring

Update several Anacapa SGPIO line names to match the existing platform
hardware design and the signal names consumed by userspace monitoring.

The previous names did not match the actual Anacapa SGPIO usage. Some
lines were named as CPU or CPU power-good signals, but they are wired
and used on Anacapa for EDSFF presence, EDSFF power-good, boot EDSFF
presence, and thermal-trip assertion monitoring.

Correct the mappings as follows:

  PWRGD_PVDDCR_SOC_P0     -> L_PRSNT_EDSFF0_N
  PWRGD_PVDDIO_P0         -> L_PRSNT_EDSFF1_N
  PWRGD_PVDDIO_MEM_S3_P0  -> R_PRSNT_EDSFF2_N
  PWRGD_CHMP_CPU0_FPGA    -> R_PRSNT_EDSFF3_N
  PWRGD_CHIL_CPU0_FPGA    -> HPM_EDSFF_PG
  EAM2_CPU_MOD_PWR_GD_R   -> PRSNT_EDSFF_BOOT_N
  CPU0_SP7R1              -> L_EDSFF0_PG
  CPU0_SP7R2              -> L_EDSFF1_PG
  CPU0_SP7R3              -> R_EDSFF2_PG
  CPU0_SP7R4              -> R_EDSFF3_PG
  HPM_AMC_THERMTRIP_R_L   -> AMC_THERMTRIP_ASSERT
  FM_CPU0_THERMTRIP_N     -> CPU_THERMTRIP_ASSERT

The left-side EDSFF slots are numbered as EDSFF0 and EDSFF1 to match
the platform slot numbering used by userspace. The thermtrip names are
also updated to describe the asserted condition monitored by userspace
instead of the raw active-low signal names.

This is a naming correction for the existing Anacapa hardware design.
There is no new board revision or underlying hardware change involved.

[arj: Tweak capitalisation in commit subject, rewrap paragraph]

Signed-off-by: Rex Fu <Rex.Fu@amd.com>
Link: https://patch.msgid.link/20260518-anacapa-sgpio-edsff-thermtrip-v2-1-e43b1847b2dc@amd.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
index 58d0651124e669f957b6e3a6b344fadd5eb147fc..1fddf3a5d1383b3af7f3f4716b5915b0d66bc972 100644 (file)
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
@@ -920,11 +920,11 @@
        "", "", "", "",
 
        /* G0-G7 line 96-111 */
-       "PWRGD_PVDDCR_SOC_P0", "",
-       "PWRGD_PVDDIO_P0", "",
-       "PWRGD_PVDDIO_MEM_S3_P0", "",
-       "PWRGD_CHMP_CPU0_FPGA", "",
-       "PWRGD_CHIL_CPU0_FPGA", "",
+       "L_PRSNT_EDSFF0_N", "",
+       "L_PRSNT_EDSFF1_N", "",
+       "R_PRSNT_EDSFF2_N", "",
+       "R_PRSNT_EDSFF3_N", "",
+       "HPM_EDSFF_PG", "",
        "PWRGD_CHEH_CPU0_FPGA", "",
        "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD",
        "", "",
@@ -946,7 +946,7 @@
        "EAM3_BRD_PRSNT_R_L", "",
        "EAM0_CPU_MOD_PWR_GD_R", "",
        "EAM1_CPU_MOD_PWR_GD_R", "",
-       "EAM2_CPU_MOD_PWR_GD_R", "",
+       "PRSNT_EDSFF_BOOT_N", "",
        "EAM3_CPU_MOD_PWR_GD_R", "",
 
        /* J0-J7 line 144-159 */
@@ -969,8 +969,8 @@
        "PDB_ALERT_R_N", "",
 
        /* L0-L7 line 176-191 */
-       "CPU0_SP7R1", "", "CPU0_SP7R2", "",
-       "CPU0_SP7R3", "", "CPU0_SP7R4", "",
+       "L_EDSFF0_PG", "", "L_EDSFF1_PG", "",
+       "R_EDSFF2_PG", "", "R_EDSFF3_PG", "",
        "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "",
        "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "",
 
@@ -996,8 +996,8 @@
        "HPM_PWR_FAIL", "Port80_b0",
        "FM_DIMM_IP_FAIL", "Port80_b1",
        "FM_DIMM_AH_FAIL", "Port80_b2",
-       "HPM_AMC_THERMTRIP_R_L", "Port80_b3",
-       "FM_CPU0_THERMTRIP_N", "Port80_b4",
+       "AMC_THERMTRIP_ASSERT", "Port80_b3",
+       "CPU_THERMTRIP_ASSERT", "Port80_b4",
        "PVDDCR_SOC_P0_OCP_L", "Port80_b5",
        "CPLD_SGPIO_RDY", "Port80_b6",
        "", "Port80_b7",