mtd: spi-nor: Make sure the QE bit is kept enabled if useful

Not all chips implement the 4BAIT table which typically indicates the
program capability, while many of them do implement the relevant SFDP
parts indicating the read capabilities. In such a situation, programs
can happen in single mode (1-1-1) and reads in quad mode (1-1-4 or
1-4-4). For the reads to work in such condition, the QE bit must be set.
In case we later use the spi_nor_write_16bit_sr_and_check() helper with
a chip with such configuration, the QE bit would get incorrectly
cleared.

Make sure this doesn't happen by keeping the QE bit under a simpler
condition:
- the quad enable hook is there (no change)
- and at least one of the two protocols is based on quad I/O cycles

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
Signed-off-by: Pratyush Yadav <pratyush@kernel.org>

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 5dd0b3cb52503300483c4f06926c742ae2794613..394c27de02d686d76d47fac05c048a38eb8366d0 100644 (file)
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -869,8 +869,8 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
                ret = spi_nor_read_cr(nor, &sr_cr[1]);
                if (ret)
                        return ret;
-       } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 &&
-                  spi_nor_get_protocol_width(nor->write_proto) == 4 &&
+       } else if ((spi_nor_get_protocol_width(nor->read_proto) == 4 ||
+                   spi_nor_get_protocol_width(nor->write_proto) == 4) &&
                   nor->params->quad_enable) {
                /*
                 * If the Status Register 2 Read command (35h) is not