m68hc11.c (m68hc11_z_replacement): Use emit_insn_after when adding the save Z instruc...

	* config/m68hc11/m68hc11.c (m68hc11_z_replacement): Use emit_insn_after
	when adding the save Z instruction so that it is part of the good BB.
	(reg_or_some_mem_operand): Do not allow the 68HC12 address indirect
	addressing mode as it is not supported by bset and bclr.
	(m68hc11_gen_movhi): Fix invalid generation of indexed indirect
	addressing with movw.
	(m68hc11_gen_movqi): Use pula and pulb instead of lda and ldb for
	68HC12.
	* config/m68hc11/m68hc11.md ("movhi_const0"): Use this pattern only
	for 68HC11.
	("*movhi_68hc12"): Handle movhi_const0.
	("*subhi3", "subqi3"): Use general_operand for operand 1.
	("*subhi3_zext"): Likewise.

From-SVN: r99403

diff --git a/gcc/config/m68hc11/m68hc11.md b/gcc/config/m68hc11/m68hc11.md
index b3063aff4a878d2472ab6277369dc5870fbb015c..83f6a23278201e42d0dbdd2516d58445f64602bb 100644 (file)
--- a/gcc/config/m68hc11/m68hc11.md
+++ b/gcc/config/m68hc11/m68hc11.md
@@ -687,8 +687,8 @@
    DONE;")
 
 (define_insn_and_split "movdf_internal"
-  [(set (match_operand:DF 0 "non_push_operand" "=mu,U,!u,U,m,m,!u")
-       (match_operand:DF 1 "general_operand" "G,iU,iU,!u,mi,!u,!mu"))
+  [(set (match_operand:DF 0 "non_push_operand" "=mu,U,m,!u,U,m,!u")
+       (match_operand:DF 1 "general_operand" "G,iU,mi,iU,!u,!u,!mu"))
    (clobber (match_scratch:HI 2 "=X,&d,&d,&d,&d,&d,&d"))]
   ""
   "#"
@@ -884,18 +884,9 @@
     }
 }")
 
-(define_insn "movhi_const0"
-  [(set (match_operand:HI 0 "splitable_operand" "=d,A,um")
-       (const_int 0))]
-  ""
-  "@
-   clra\\n\\tclrb
-   ld%0\\t#0
-   clr\\t%b0\\n\\tclr\\t%h0")
-
 (define_insn "*movhi_68hc12"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=U,dAw,dAw,U,U,m,!u")
-       (match_operand:HI 1 "general_operand" "U,dAwim,!u,dAwi,!u,dAw,riU"))]
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=U,dAw,dAw,m,U,U,m,!u")
+       (match_operand:HI 1 "general_operand" "U,dAwim,!u,K,dAwi,!u,dAw,riU"))]
   "TARGET_M6812"
   "*
 {
@@ -903,6 +894,15 @@
   return \"\";
 }")
 
+(define_insn "movhi_const0"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,A,um")
+       (const_int 0))]
+  "TARGET_M6811"
+  "@
+   clra\\n\\tclrb
+   ld%0\\t#0
+   clr\\t%b0\\n\\tclr\\t%h0")
+
 (define_insn "*movhi_m68hc11"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=dAw,!u,m,m,dAw,!*u")
        (match_operand:HI 1 "general_operand" "dAwim,dAw,dA,?Aw,!*u,dAw"))]
@@ -1235,7 +1235,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=m,m,!u,!u")
        (zero_extend:DI 
            (match_operand:SI 1 "nonimmediate_operand" "m,Du,m,Du")))
-   (clobber (match_scratch:HI 2 "=d,d,&d,d"))]
+   (clobber (match_scratch:HI 2 "=d,d,d,d"))]
   ""
   "#")
 
@@ -2380,7 +2380,7 @@
   [(set (match_operand:HI 0 "hard_reg_operand" "=A,d")
        (plus:HI (zero_extend:HI 
                     (match_operand:QI 1 "nonimmediate_operand" "d,um*A"))
-                (match_operand:HI 2 "hard_reg_operand" "0,0")))]
+                (match_operand:HI 2 "general_operand" "0,0")))]
   ""
   "*
 {
@@ -2714,7 +2714,7 @@
 
 (define_insn "*subhi3"
   [(set (match_operand:HI 0 "register_operand" "=d,*A,d,*A")
-       (minus:HI (match_operand:HI 1 "register_operand" "0,0,0,0")
+       (minus:HI (match_operand:HI 1 "general_operand" "0,0,0,0")
                  (match_operand:HI 2 "general_operand" "im*A*d,im*d*A,u,!u")))]
   ""
   "*
@@ -2729,7 +2729,7 @@
 
 (define_insn "*subhi3_zext"
   [(set (match_operand:HI 0 "hard_reg_operand" "=d,d")
-       (minus:HI (match_operand:HI 1 "hard_reg_operand" "0,0")
+       (minus:HI (match_operand:HI 1 "general_operand" "0,0")
            (zero_extend:HI (match_operand:QI 2 "general_operand" "mi*A,!u"))))]
   ""
   "*
@@ -2749,7 +2749,7 @@
 
 (define_insn "subqi3"
   [(set (match_operand:QI 0 "hard_reg_operand" "=dq,!*x*y")
-        (minus:QI (match_operand:QI 1 "hard_reg_operand" "0,0")
+        (minus:QI (match_operand:QI 1 "general_operand" "0,0")
                   (match_operand:QI 2 "general_operand" "uim*A*d,uim*A*d")))]
   ""
   "*
@@ -3324,8 +3324,8 @@
 
 (define_insn "*andqi3_gen"
   [(set (match_operand:QI 0 "register_operand" "=d,d,d,?*A,?*A,!*q")
-        (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0")
-             (match_operand:QI 2 "general_operand" "mi,!u,?*A,!um,?*A*d,!um*A")))]
+        (and:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0")
+             (match_operand:QI 2 "general_operand" "mi,!*u,?*A,!*um,?*A*d,!*um*A")))]
   ""
   "*
 {
@@ -3542,8 +3542,8 @@
 
 (define_insn "*iorqi3_gen"
   [(set (match_operand:QI 0 "register_operand" "=d,d,d,?*A,?*A,!*q")
-       (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0")
-            (match_operand:QI 2 "general_operand" "mi,!u,!*A,!um,?*A*d,!um*A")))]
+       (ior:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0")
+            (match_operand:QI 2 "general_operand" "mi,!*u,!*A,!*um,?*A*d,!*um*A")))]
   ""
   "*
 {
@@ -3634,8 +3634,8 @@
 
 (define_insn "xorqi3"
   [(set (match_operand:QI 0 "register_operand" "=d,d,d,?*A,?*A,!*q")
-        (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0")
-             (match_operand:QI 2 "general_operand" "im,!u,!*A,!ium,?*A*d,!ium*A")))]
+        (xor:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0")
+             (match_operand:QI 2 "general_operand" "im,!*u,!*A,!i*um,?*A*d,!i*um*A")))]
   ""
   "*
 {
@@ -6909,14 +6909,16 @@
 ;;
 ;; Replace "leas 2,sp" with a "pulx" or a "puly".
 ;; On 68HC12, this is one cycle slower but one byte smaller.
-;; pr target/6899: This peephole is not valid because a register CSE
-;; pass removes the pulx/puly.
+;; pr target/6899: This peephole was not valid because a register CSE
+;; pass removes the pulx/puly.  The 'use' clause ensure that the pulx is
+;; not removed.
 ;;
 (define_peephole2
   [(set (reg:HI SP_REGNUM) (plus:HI (reg:HI SP_REGNUM) (const_int 2)))
    (match_scratch:HI 0 "xy")]
-  "0 && TARGET_M6812 && optimize_size"
-  [(set (match_dup 0) (match_dup 1))]
+  "TARGET_M6812 && optimize_size"
+  [(set (match_dup 0) (match_dup 1))
+   (use (match_dup 0))]
   "operands[1] = gen_rtx (MEM, HImode,
                          gen_rtx (POST_INC, HImode,
                                   gen_rtx_REG (HImode, HARD_SP_REGNUM)));")