clk: qcom: dispcc-sc8280xp: Use ret registers on GDSCs

[ Upstream commit 20e1d75bc043c5ec1fd8f5169fde17db89eb11c3 ]

The DISP_CC GDSCs have not been instructed to use the ret registers.
Fix that.

Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230725-topic-8280_dispcc_gdsc-v1-1-236590060531@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-sc8280xp.c
index 167470beb36915cbf9864fea706faedfd0e938b5..30f636b9f0ec893dca5e4fc81d328dd3e4e80d0c 100644 (file)
--- a/drivers/clk/qcom/dispcc-sc8280xp.c
+++ b/drivers/clk/qcom/dispcc-sc8280xp.c
@@ -3057,7 +3057,7 @@ static struct gdsc disp0_mdss_gdsc = {
                .name = "disp0_mdss_gdsc",
        },
        .pwrsts = PWRSTS_OFF_ON,
-       .flags = HW_CTRL,
+       .flags = HW_CTRL | RETAIN_FF_ENABLE,
 };
 
 static struct gdsc disp1_mdss_gdsc = {
@@ -3069,7 +3069,7 @@ static struct gdsc disp1_mdss_gdsc = {
                .name = "disp1_mdss_gdsc",
        },
        .pwrsts = PWRSTS_OFF_ON,
-       .flags = HW_CTRL,
+       .flags = HW_CTRL | RETAIN_FF_ENABLE,
 };
 
 static struct gdsc disp0_mdss_int2_gdsc = {
@@ -3081,7 +3081,7 @@ static struct gdsc disp0_mdss_int2_gdsc = {
                .name = "disp0_mdss_int2_gdsc",
        },
        .pwrsts = PWRSTS_OFF_ON,
-       .flags = HW_CTRL,
+       .flags = HW_CTRL | RETAIN_FF_ENABLE,
 };
 
 static struct gdsc disp1_mdss_int2_gdsc = {
@@ -3093,7 +3093,7 @@ static struct gdsc disp1_mdss_int2_gdsc = {
                .name = "disp1_mdss_int2_gdsc",
        },
        .pwrsts = PWRSTS_OFF_ON,
-       .flags = HW_CTRL,
+       .flags = HW_CTRL | RETAIN_FF_ENABLE,
 };
 
 static struct gdsc *disp0_cc_sc8280xp_gdscs[] = {