drm/amdgpu/gfx10: re-emit unprocessed state on ring reset

Re-emit the unprocessed state after resetting the queue.
Drop the soft_recovery callbacks as the queue reset replaces
it.

Reviewed-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 506454ed27bde68ca86be0f3d0c1a7b3e9a174fa..744f51a6f522d5fee183f4026db604891d1a180f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9050,21 +9050,6 @@ static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
                                                           ref, mask);
 }
 
-static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
-                                        unsigned int vmid)
-{
-       struct amdgpu_device *adev = ring->adev;
-       uint32_t value = 0;
-
-       value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
-       value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
-       value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
-       value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
-       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
-       WREG32_SOC15(GC, 0, mmSQ_CMD, value);
-       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
-}
-
 static void
 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
                                      uint32_t me, uint32_t pipe,
@@ -9544,7 +9529,7 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
        if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
                return -EINVAL;
 
-       drm_sched_wqueue_stop(&ring->sched);
+       amdgpu_ring_reset_helper_begin(ring, timedout_fence);
 
        spin_lock_irqsave(&kiq->ring_lock, flags);
 
@@ -9593,12 +9578,7 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
        if (r)
                return r;
 
-       r = amdgpu_ring_test_ring(ring);
-       if (r)
-               return r;
-       amdgpu_fence_driver_force_completion(ring);
-       drm_sched_wqueue_start(&ring->sched);
-       return 0;
+       return amdgpu_ring_reset_helper_end(ring, timedout_fence);
 }
 
 static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
@@ -9617,7 +9597,7 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
        if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
                return -EINVAL;
 
-       drm_sched_wqueue_stop(&ring->sched);
+       amdgpu_ring_reset_helper_begin(ring, timedout_fence);
 
        spin_lock_irqsave(&kiq->ring_lock, flags);
 
@@ -9671,12 +9651,7 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
        if (r)
                return r;
 
-       r = amdgpu_ring_test_ring(ring);
-       if (r)
-               return r;
-       amdgpu_fence_driver_force_completion(ring);
-       drm_sched_wqueue_start(&ring->sched);
-       return 0;
+       return amdgpu_ring_reset_helper_end(ring, timedout_fence);
 }
 
 static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
@@ -9911,7 +9886,6 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
        .emit_wreg = gfx_v10_0_ring_emit_wreg,
        .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
-       .soft_recovery = gfx_v10_0_ring_soft_recovery,
        .emit_mem_sync = gfx_v10_0_emit_mem_sync,
        .reset = gfx_v10_0_reset_kgq,
        .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
@@ -9952,7 +9926,6 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
        .emit_wreg = gfx_v10_0_ring_emit_wreg,
        .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
-       .soft_recovery = gfx_v10_0_ring_soft_recovery,
        .emit_mem_sync = gfx_v10_0_emit_mem_sync,
        .reset = gfx_v10_0_reset_kcq,
        .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,