arm64: dts: renesas: rzt2h-n2h-evk: Enable xSPI nodes

Enable the xSPI0 and xSPI1 controllers on the RZ/T2H N2H EVK board.

Configure the xSPI0 controller interface to 1-bit (x1) mode, even though
the connected MX25LW51245 octal flash device supports octal mode.  Add a
corresponding inline hardware comment detailing this restriction;
operating in octal mode causes the BootROM to fail loading the
first-stage bootloader following a Watchdog Timer (WDT) reset.

Configure the xSPI1 controller interface connected to the AT25SF128A
flash device for 4-bit (x4) mode to utilize all available data lines.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260527202430.606341-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index 4c0e52850ca972505a8528bb645e038c48e22375..e9ed2de128f6f2e9e02843f746b9e01e3b48debc 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -345,3 +345,18 @@
        };
 };
 
+/*
+ * XSPI0 Pin Configuration:
+ * ------------------------
+ * Signal     | Pin     | SW5
+ * -----------|---------|---------------
+ * XSPI0_ECS  | P07_5   | 5: OFF, 6: ON
+ */
+&xspi0_pins {
+       ecs-pins {
+               pinmux = <RZT2H_PORT_PINMUX(7, 5, 0x1c)>; /* XSPI0_ECS0 */
+               drive-strength-microamp = <2500>;
+               input-schmitt-disable;
+               slew-rate = <0>;
+       };
+};

diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index ba0f5d12772c7524ae01b50c9799d4b086d8f8cb..e86e6d3aa8a34c9f608b1302d2177a66fb481a96 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -5,6 +5,7 @@
  * Copyright (C) 2025 Renesas Electronics Corp.
  */
 
+#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/net/mscc-phy-vsc8531.h>
@@ -20,6 +21,8 @@
                mmc0 = &sdhi0;
                mmc1 = &sdhi1;
                serial0 = &sci0;
+               spi0 = &xspi0;
+               spi1 = &xspi1;
        };
 
        chosen {
@@ -456,6 +459,45 @@
                        input-schmitt-disable;
                };
        };
+
+       xspi0_pins: xspi0-group {
+               ctrl-data-pins {
+                       pinmux = <RZT2H_PORT_PINMUX(5, 1, 0x1c)>, /* XSPI0_CKP */
+                                <RZT2H_PORT_PINMUX(5, 3, 0x1c)>, /* XSPI0_CS0 */
+                                <RZT2H_PORT_PINMUX(5, 5, 0x1c)>, /* XSPI0_DS */
+                                <RZT2H_PORT_PINMUX(5, 6, 0x1c)>, /* XSPI0_IO0 */
+                                <RZT2H_PORT_PINMUX(5, 7, 0x1c)>, /* XSPI0_IO1 */
+                                <RZT2H_PORT_PINMUX(6, 0, 0x1c)>, /* XSPI0_IO2 */
+                                <RZT2H_PORT_PINMUX(6, 1, 0x1c)>, /* XSPI0_IO3 */
+                                <RZT2H_PORT_PINMUX(6, 2, 0x1c)>, /* XSPI0_IO4 */
+                                <RZT2H_PORT_PINMUX(6, 3, 0x1c)>, /* XSPI0_IO5 */
+                                <RZT2H_PORT_PINMUX(6, 4, 0x1c)>, /* XSPI0_IO6 */
+                                <RZT2H_PORT_PINMUX(6, 5, 0x1c)>, /* XSPI0_IO7 */
+                                <RZT2H_PORT_PINMUX(6, 6, 0x1c)>; /* XSPI0_RESET0 */
+                       drive-strength-microamp = <9000>;
+                       input-schmitt-disable;
+                       slew-rate = <1>;
+               };
+       };
+
+       /*
+        * XSPI1 Pin Configuration:
+        * ------------------------
+        * Signal     | Pin      | RZ/T2H (SW1)  | RZ/N2H (DSW2)
+        * -----------|----------|---------------|---------------
+        * ALL        | Multiple | 6: ON         | 6: ON
+        */
+       xspi1_pins: xspi1-pins {
+               pinmux = <RZT2H_PORT_PINMUX(1, 0, 0x1c)>, /* XSPI1_CKP */
+                        <RZT2H_PORT_PINMUX(1, 1, 0x1c)>, /* XSPI1_CS0 */
+                        <RZT2H_PORT_PINMUX(1, 4, 0x1c)>, /* XSPI1_IO0 */
+                        <RZT2H_PORT_PINMUX(1, 5, 0x1c)>, /* XSPI1_IO1 */
+                        <RZT2H_PORT_PINMUX(1, 6, 0x1c)>, /* XSPI1_IO2 */
+                        <RZT2H_PORT_PINMUX(1, 7, 0x1c)>; /* XSPI1_IO3 */
+               drive-strength-microamp = <9000>;
+               input-schmitt-enable;
+               slew-rate = <1>;
+       };
 };
 
 &sci0 {
@@ -520,3 +562,88 @@
        timeout-sec = <60>;
 };
 
+&xspi0 {
+       pinctrl-0 = <&xspi0_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       assigned-clocks = <&cpg CPG_CORE R9A09G077_XSPI_CLK0>;
+       assigned-clock-rates = <50000000>;
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               vcc-supply = <&reg_3p3v>;
+               m25p,fast-read;
+               /*
+                * Configure for 1-bit mode to prevent the BootROM from failing
+                * to load the first-stage bootloader following a watchdog reset.
+                */
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <1>;
+               spi-max-frequency = <50000000>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "bl2-0";
+                               reg = <0x00000000 0x00060000>;
+                               read-only;
+                       };
+
+                       partition@60000 {
+                               label = "fip-0";
+                               reg = <0x00060000 0x007a0000>;
+                               read-only;
+                       };
+
+                       partition@800000 {
+                               label = "user-0";
+                               reg = <0x800000 0x003800000>;
+                       };
+               };
+       };
+};
+
+&xspi1 {
+       pinctrl-0 = <&xspi1_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       assigned-clocks = <&cpg CPG_CORE R9A09G077_XSPI_CLK1>;
+       assigned-clock-rates = <50000000>;
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               vcc-supply = <&reg_3p3v>;
+               m25p,fast-read;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+               spi-max-frequency = <50000000>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "bl2-1";
+                               reg = <0x00000000 0x00060000>;
+                       };
+
+                       partition@60000 {
+                               label = "fip-1";
+                               reg = <0x00060000 0x007a0000>;
+                       };
+
+                       partition@800000 {
+                               label = "user-1";
+                               reg = <0x800000 0x800000>;
+                       };
+               };
+       };
+};