arm64: dts: renesas: r9a09g087: Fix CPG register region sizes

The CPG register regions were incorrectly sized.  Update them to match
the actual hardware specification:
  - First region (0x80280000): 0x1000 -> 0x10000 (64kiB)
  - Second region (0x81280000): 0x9000 -> 0x10000 (64kiB)

Fixes: 4b3d31f0b81fe ("arm64: dts: renesas: Add initial SoC DTSI for the RZ/N2H SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260213131742.3606334-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index 4a133956133218c1f0f2f15a2ed48e3f611976de..d407c48f996695a0cd5a83ee5b078a3de0ca1f84 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -977,8 +977,8 @@
 
                cpg: clock-controller@80280000 {
                        compatible = "renesas,r9a09g087-cpg-mssr";
-                       reg = <0 0x80280000 0 0x1000>,
-                             <0 0x81280000 0 0x9000>;
+                       reg = <0 0x80280000 0 0x10000>,
+                             <0 0x81280000 0 0x10000>;
                        clocks = <&extal_clk>;
                        clock-names = "extal";
                        #clock-cells = <2>;