parisc: Add memory clobber to TLB purges

commit 44224bdb99150ad17cf394973b25736cb92c246a upstream.

The pdtlb and pitlb instructions are strongly ordered. The asms invoking
these instructions should be compiler memory barriers to ensure the
compiler doesn't reorder memory operations around these instructions.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
CC: stable@vger.kernel.org # v4.20+
Fixes: 3847dab77421 ("parisc: Add alternative coding infrastructure")
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h
index 006fb939cac8801c20cafff55fb713b823dfac59..c18351cf58762d4a416be433c435464e1cbccb0c 100644 (file)
--- a/arch/parisc/include/asm/cache.h
+++ b/arch/parisc/include/asm/cache.h
@@ -44,14 +44,14 @@ void parisc_setup_cache_timing(void);
 
 #define pdtlb(addr)    asm volatile("pdtlb 0(%%sr1,%0)" \
                        ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
-                       : : "r" (addr))
+                       : : "r" (addr) : "memory")
 #define pitlb(addr)    asm volatile("pitlb 0(%%sr1,%0)" \
                        ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
                        ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \
-                       : : "r" (addr))
+                       : : "r" (addr) : "memory")
 #define pdtlb_kernel(addr)  asm volatile("pdtlb 0(%0)"   \
                        ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
-                       : : "r" (addr))
+                       : : "r" (addr) : "memory")
 
 #define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \
                        ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \