arm64: dts: qcom: kaanapali: Add header file for IPCC physical client IDs

On earlier platforms, Inter Process Communication Controller (IPCC) used
virtual client IDs and performed virtual-to-physical mapping in hardware,
so the IDs defined in dt-bindings/mailbox/qcom-ipcc.h are common across
platforms. Physical client IDs instead of virtual client IDs are used for
qcom new platforms like Kaanapali, which will be parsed by the devicetree
and passed to hardware to use Physical client IDs directly. Since physical
client IDs could vary across platforms, add a corresponding header file
for the Kaanapali platform.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251031-knp-ipcc-v3-2-62ffb4168dff@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h b/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h
new file mode 100644 (file)
index 0000000..125375a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DTS_KAANAPALI_MAILBOX_IPCC_H
+#define __DTS_KAANAPALI_MAILBOX_IPCC_H
+
+/* Physical client IDs */
+#define IPCC_MPROC_AOP                 0
+#define IPCC_MPROC_TZ                  1
+#define IPCC_MPROC_MPSS                        2
+#define IPCC_MPROC_LPASS               3
+#define IPCC_MPROC_SDC                 4
+#define IPCC_MPROC_CDSP                        5
+#define IPCC_MPROC_APSS                        6
+#define IPCC_MPROC_SOCCP               13
+#define IPCC_MPROC_DCP                 14
+#define IPCC_MPROC_SPSS                        15
+#define IPCC_MPROC_TME                 16
+#define IPCC_MPROC_WPSS                        17
+
+#define IPCC_COMPUTE_L0_CDSP           2
+#define IPCC_COMPUTE_L0_APSS           3
+#define IPCC_COMPUTE_L0_GPU            4
+#define IPCC_COMPUTE_L0_CVP            8
+#define IPCC_COMPUTE_L0_CAM            9
+#define IPCC_COMPUTE_L0_CAM1           10
+#define IPCC_COMPUTE_L0_DCP            11
+#define IPCC_COMPUTE_L0_VPU            12
+#define IPCC_COMPUTE_L0_SOCCP          16
+
+#define IPCC_COMPUTE_L1_CDSP           2
+#define IPCC_COMPUTE_L1_APSS           3
+#define IPCC_COMPUTE_L1_GPU            4
+#define IPCC_COMPUTE_L1_CVP            8
+#define IPCC_COMPUTE_L1_CAM            9
+#define IPCC_COMPUTE_L1_CAM1           10
+#define IPCC_COMPUTE_L1_DCP            11
+#define IPCC_COMPUTE_L1_VPU            12
+#define IPCC_COMPUTE_L1_SOCCP          16
+
+#define IPCC_PERIPH_CDSP               2
+#define IPCC_PERIPH_APSS               3
+#define IPCC_PERIPH_PCIE0              4
+#define IPCC_PERIPH_PCIE1              5
+
+#define IPCC_FENCE_CDSP                        2
+#define IPCC_FENCE_APSS                        3
+#define IPCC_FENCE_GPU                 4
+#define IPCC_FENCE_CVP                 8
+#define IPCC_FENCE_CAM                 8
+#define IPCC_FENCE_CAM1                        10
+#define IPCC_FENCE_DCP                 11
+#define IPCC_FENCE_VPU                 20
+#define IPCC_FENCE_SOCCP               24
+
+#endif