drm/msm/dpu: drop intr_start from DPU 3.x catalog files

DPU 3.x don't have separate intr_start interrupt, drop it from catalog
files.

Fixes: 94391a14fc27 ("drm/msm/dpu1: Add MSM8998 to hw catalog")
Fixes: 7204df5e7e68 ("drm/msm/dpu: add support for SDM660 and SDM630 platforms")
Patchwork: https://patchwork.freedesktop.org/patch/696488/
Link: https://lore.kernel.org/r/20251228-mdp5-drop-dpu3-v4-1-7497c3d39179@oss.qualcomm.com
Tested-by: Alexey Minnekhanov <alexeymin@minlexx.ru>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index f91220496082bd101099c1817c41699215980d53..b1b03d8b30fa0cb8a3a1a73e928bec98e3fd2a98 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -42,24 +42,19 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x1000, .len = 0x94,
                .features = BIT(DPU_CTL_SPLIT_DISPLAY),
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        }, {
                .name = "ctl_1", .id = CTL_1,
                .base = 0x1200, .len = 0x94,
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        }, {
                .name = "ctl_2", .id = CTL_2,
                .base = 0x1400, .len = 0x94,
                .features = BIT(DPU_CTL_SPLIT_DISPLAY),
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
        }, {
                .name = "ctl_3", .id = CTL_3,
                .base = 0x1600, .len = 0x94,
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
        }, {
                .name = "ctl_4", .id = CTL_4,
                .base = 0x1800, .len = 0x94,
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
index 8f9a097147c02b538e720dd52f77e705f7ff1ca2..64df4e80ea43deaffd0e5e20defd2c8e69c35d1b 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
@@ -37,24 +37,19 @@ static const struct dpu_ctl_cfg sdm660_ctl[] = {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x1000, .len = 0x94,
                .features = BIT(DPU_CTL_SPLIT_DISPLAY),
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        }, {
                .name = "ctl_1", .id = CTL_1,
                .base = 0x1200, .len = 0x94,
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        }, {
                .name = "ctl_2", .id = CTL_2,
                .base = 0x1400, .len = 0x94,
                .features = BIT(DPU_CTL_SPLIT_DISPLAY),
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
        }, {
                .name = "ctl_3", .id = CTL_3,
                .base = 0x1600, .len = 0x94,
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
        }, {
                .name = "ctl_4", .id = CTL_4,
                .base = 0x1800, .len = 0x94,
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
index 0ad18bd273ff8c080f001f0bee654393cf0c24cd..b409af899918203a33ef795a1db18ac2c0e72e49 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
@@ -36,24 +36,19 @@ static const struct dpu_ctl_cfg sdm630_ctl[] = {
                .name = "ctl_0", .id = CTL_0,
                .base = 0x1000, .len = 0x94,
                .features = BIT(DPU_CTL_SPLIT_DISPLAY),
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        }, {
                .name = "ctl_1", .id = CTL_1,
                .base = 0x1200, .len = 0x94,
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
        }, {
                .name = "ctl_2", .id = CTL_2,
                .base = 0x1400, .len = 0x94,
                .features = BIT(DPU_CTL_SPLIT_DISPLAY),
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
        }, {
                .name = "ctl_3", .id = CTL_3,
                .base = 0x1600, .len = 0x94,
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
        }, {
                .name = "ctl_4", .id = CTL_4,
                .base = 0x1800, .len = 0x94,
-               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
        },
 };