arm64: dts: qcom: sm8750: Fix DSI1 phy reference clock rate

The DSI PHY CXO clock input is the SoC CXO divided by two.  DSI0 already
uses correct one, but DSI1 got copy-paste from SM8650.  Wrong clock
parent will cause incorrect DSI1 PHY PLL frequencies to be used making
the DSI panel non-working, although there is no upstream user of DSI1.

Fixes: 818ae2b389bc ("arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260331165645.233965-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 49d4a9a34c04bb832c3aa99b82efb309e876674c..70830cb49e73a3d586ccccd82208ed621f54d008 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -3340,7 +3340,7 @@
                                            "dsi_pll";
 
                                clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                                        <&rpmhcc RPMH_CXO_CLK>;
+                                        <&bi_tcxo_div2>;
                                clock-names = "iface",
                                              "ref";