PCI: tegra194: Calibrate pipe to UPHY for Endpoint mode

Calibrate 'Pipe to Universal PHY(UPHY)' (P2U) for the Endpoint controller
to request UPHY PLL rate change to 2.5GT/s (Gen 1) during initialization.
This helps to reset stale PLL state from the previous bad link state.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Link: https://patch.msgid.link/20260324191000.1095768-3-mmaddireddy@nvidia.com

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 002945de5e1171b580194bdbaa7299d34056a4b0..7f74d72a21dd3da94430d85a31158937faed0c02 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1072,6 +1072,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
                ret = phy_power_on(pcie->phys[i]);
                if (ret < 0)
                        goto phy_exit;
+
+               if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
+                       phy_calibrate(pcie->phys[i]);
        }
 
        return 0;