};
/**
- * struct dw_edma_core_ops - platform-specific eDMA methods
+ * struct dw_edma_plat_ops - platform-specific eDMA methods
* @irq_vector: Get IRQ number of the passed eDMA channel. Note the
* method accepts the channel id in the end-to-end
* numbering with the eDMA write channels being placed
/**
* struct dw_edma_chip - representation of DesignWare eDMA controller hardware
* @dev: struct device of the eDMA controller
- * @id: instance ID
* @nr_irqs: total number of DMA IRQs
- * @ops DMA channel to IRQ number mapping
- * @flags dw_edma_chip_flags
- * @reg_base DMA register base address
- * @ll_wr_cnt DMA write link list count
- * @ll_rd_cnt DMA read link list count
- * @rg_region DMA register region
- * @ll_region_wr DMA descriptor link list memory for write channel
- * @ll_region_rd DMA descriptor link list memory for read channel
- * @dt_region_wr DMA data memory for write channel
- * @dt_region_rd DMA data memory for read channel
- * @mf DMA register map format
+ * @ops: DMA channel to IRQ number mapping
+ * @flags: dw_edma_chip_flags
+ * @reg_base: DMA register base address
+ * @ll_wr_cnt: DMA write link list count
+ * @ll_rd_cnt: DMA read link list count
+ * @ll_region_wr: DMA descriptor link list memory for write channel
+ * @ll_region_rd: DMA descriptor link list memory for read channel
+ * @dt_region_wr: DMA data memory for write channel
+ * @dt_region_rd: DMA data memory for read channel
+ * @mf: DMA register map format
* @dw: struct dw_edma that is filled by dw_edma_probe()
*/
struct dw_edma_chip {