arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588

Add the vdpu381 Video Decoders to the rk3588-base devicetree.

The RK3588 based SoCs all embed 2 vdpu381 decoders.
This also adds the dedicated IOMMU controllers.

Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Link: https://patch.msgid.link/20251020212009.8852-2-detlev.casanova@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 2a79217930206bd1b8097c8effda5877c0557551..aa74e8d7b4e95751e9e5a6723a330e0cf42341d9 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1353,6 +1353,70 @@
                #iommu-cells = <0>;
        };
 
+       vdec0: video-codec@fdc38000 {
+               compatible = "rockchip,rk3588-vdec";
+               reg = <0x0 0xfdc38100 0x0 0x500>,
+                     <0x0 0xfdc38000 0x0 0x100>,
+                     <0x0 0xfdc38600 0x0 0x100>;
+               reg-names = "function", "link", "cache";
+               interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>,
+                        <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>;
+               clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+               assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
+                                 <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
+               assigned-clock-rates = <800000000>, <600000000>,
+                                      <600000000>, <1000000000>;
+               iommus = <&vdec0_mmu>;
+               power-domains = <&power RK3588_PD_RKVDEC0>;
+               resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>,
+                        <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>;
+               reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+               sram = <&vdec0_sram>;
+       };
+
+       vdec0_mmu: iommu@fdc38700 {
+               compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+               reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>;
+               interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>;
+               clock-names = "aclk", "iface";
+               power-domains = <&power RK3588_PD_RKVDEC0>;
+               #iommu-cells = <0>;
+       };
+
+       vdec1: video-codec@fdc40000 {
+               compatible = "rockchip,rk3588-vdec";
+               reg = <0x0 0xfdc40100 0x0 0x500>,
+                     <0x0 0xfdc40000 0x0 0x100>,
+                     <0x0 0xfdc40600 0x0 0x100>;
+               reg-names = "function", "link", "cache";
+               interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>,
+                        <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>;
+               clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+               assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
+                                 <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
+               assigned-clock-rates = <800000000>, <600000000>,
+                                      <600000000>, <1000000000>;
+               iommus = <&vdec1_mmu>;
+               power-domains = <&power RK3588_PD_RKVDEC1>;
+               resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>,
+                        <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>;
+               reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+               sram = <&vdec1_sram>;
+       };
+
+       vdec1_mmu: iommu@fdc40700 {
+               compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+               reg = <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>;
+               interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>;
+               clock-names = "aclk", "iface";
+               power-domains = <&power RK3588_PD_RKVDEC1>;
+               #iommu-cells = <0>;
+       };
+
        av1d: video-codec@fdc70000 {
                compatible = "rockchip,rk3588-av1-vpu";
                reg = <0x0 0xfdc70000 0x0 0x800>;
@@ -3249,6 +3313,16 @@
                ranges = <0x0 0x0 0xff001000 0xef000>;
                #address-cells = <1>;
                #size-cells = <1>;
+
+               vdec0_sram: codec-sram@0 {
+                       reg = <0x0 0x78000>;
+                       pool;
+               };
+
+               vdec1_sram: codec-sram@78000 {
+                       reg = <0x78000 0x77000>;
+                       pool;
+               };
        };
 
        pinctrl: pinctrl {