arm64: dts: rockchip: Fix rk356x PCIe range mappings

The pcie bus address should be mapped 1:1 to the cpu side MMIO address, so
that there is no same address allocated from normal system memory. Otherwise
it's broken if the same address assigned to the EP for DMA purpose.Fix it to
sync with the vendor BSP.

Fixes: 568a67e742df ("arm64: dts: rockchip: Fix rk356x PCIe register and range mappings")
Fixes: 66b51ea7d70f ("arm64: dts: rockchip: Add rk3568 PCIe2x1 controller")
Cc: stable@vger.kernel.org
Cc: Andrew Powers-Holmes <aholmes@omnom.net>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/1767600929-195341-1-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index e719a3df126c59ce532d3e26cf358fd2160c1d9c..658097ed69714a82f6e7e8870bc35fc285ad1b86 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -185,7 +185,7 @@
                      <0x0 0xf2000000 0x0 0x00100000>;
                ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
                         <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
-                        <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
+                        <0x03000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>;
                reg-names = "dbi", "apb", "config";
                resets = <&cru SRST_PCIE30X1_POWERUP>;
                reset-names = "pipe";
@@ -238,7 +238,7 @@
                      <0x0 0xf0000000 0x0 0x00100000>;
                ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
                         <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
-                        <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
+                        <0x03000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>;
                reg-names = "dbi", "apb", "config";
                resets = <&cru SRST_PCIE30X2_POWERUP>;
                reset-names = "pipe";

diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
index 8893b7b6cc9ff3fe337786103be2854230f6fa9a..a2c4957a589921ee47fa98df11486443dd48ce58 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
@@ -1022,7 +1022,7 @@
                power-domains = <&power RK3568_PD_PIPE>;
                ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
                         <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
-                        <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
+                        <0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
                resets = <&cru SRST_PCIE20_POWERUP>;
                reset-names = "pipe";
                #address-cells = <3>;