# define ARM_CPU_IMP_ARM 0x41
# define HISI_CPU_IMP 0x48
+# define ARM_CPU_IMP_APPLE 0x61
# define ARM_CPU_PART_CORTEX_A72 0xD08
# define ARM_CPU_PART_N1 0xD0C
# define HISI_CPU_PART_KP920 0xD01
# define ARM_CPU_PART_V2 0xD4F
+# define APPLE_CPU_PART_M1_ICESTORM 0x022
+# define APPLE_CPU_PART_M1_FIRESTORM 0x023
+# define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
+# define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
+# define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
+# define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
+# define APPLE_CPU_PART_M2_BLIZZARD 0x032
+# define APPLE_CPU_PART_M2_AVALANCHE 0x033
+# define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034
+# define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035
+# define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038
+# define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039
+
# define MIDR_PARTNUM_SHIFT 4
# define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT)
# define MIDR_PARTNUM(midr) \
} else { \
ctx->meth = sha3_generic_md; \
}
+#elif defined(__aarch64__)
+# include "arm_arch.h"
+
+static sha3_absorb_fn armsha3_sha3_absorb;
+
+size_t SHA3_absorb_cext(uint64_t A[5][5], const unsigned char *inp, size_t len,
+ size_t r);
+/*-
+ * Hardware-assisted ARMv8.2 SHA3 extension version of the absorb()
+ */
+static size_t armsha3_sha3_absorb(void *vctx, const void *inp, size_t len)
+{
+ KECCAK1600_CTX *ctx = vctx;
+
+ return SHA3_absorb_cext(ctx->A, inp, len, ctx->block_size);
+}
+
+static PROV_SHA3_METHOD sha3_ARMSHA3_md =
+{
+ armsha3_sha3_absorb,
+ generic_sha3_final
+};
+/* Detection on Apple operating systems */
+# if defined(__APPLE__)
+# define ARM_SHA3_CAPABLE (OPENSSL_armcap_P & ARMV8_SHA3)
+# define SHA3_SET_MD(uname, typ) \
+ if (ARM_SHA3_CAPABLE) { \
+ ctx->meth = sha3_ARMSHA3_md; \
+ } else { \
+ ctx->meth = sha3_generic_md; \
+ }
+# define KMAC_SET_MD(bitlen) \
+ if (ARM_SHA3_CAPABLE) { \
+ ctx->meth = sha3_ARMSHA3_md; \
+ } else { \
+ ctx->meth = sha3_generic_md; \
+ }
+/* Detection on other operating systems */
+# else
+# define ARM_HAS_FASTER_SHA3 \
+ (MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM) ||\
+ MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO) ||\
+ MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX) ||\
+ MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE) ||\
+ MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO) ||\
+ MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX))
+# define SHA3_SET_MD(uname, typ) \
+ if (ARM_HAS_FASTER_SHA3) { \
+ ctx->meth = sha3_ARMSHA3_md; \
+ } else { \
+ ctx->meth = sha3_generic_md; \
+ }
+# define KMAC_SET_MD(bitlen) \
+ if (ARM_HAS_FASTER_SHA3) { \
+ ctx->meth = sha3_ARMSHA3_md; \
+ } else { \
+ ctx->meth = sha3_generic_md; \
+ }
+# endif /* APPLE */
#else
# define SHA3_SET_MD(uname, typ) ctx->meth = sha3_generic_md;
# define KMAC_SET_MD(bitlen) ctx->meth = sha3_generic_md;