LoongArch: Remove the definition of ISA_BASE_LA64V110 from the code.

The instructions defined in LoongArch Reference Manual v1.1 are not the instruction
set v1.1 version. The CPU defined later may only support some instructions in
LoongArch Reference Manual v1.1. Therefore, the macro ISA_BASE_LA64V110 and
related definitions are removed here.

gcc/ChangeLog:

	* config/loongarch/genopts/loongarch-strings: Delete STR_ISA_BASE_LA64V110.
	* config/loongarch/genopts/loongarch.opt.in: Likewise.
	* config/loongarch/loongarch-cpu.cc (ISA_BASE_LA64V110_FEATURES): Delete macro.
	(fill_native_cpu_config): Define a new variable hw_isa_evolution record the
	extended instruction set support read from cpucfg.
	* config/loongarch/loongarch-def.cc: Set evolution at initialization.
	* config/loongarch/loongarch-def.h (ISA_BASE_LA64V100): Delete.
	(ISA_BASE_LA64V110): Likewise.
	(N_ISA_BASE_TYPES): Likewise.
	(defined): Likewise.
	* config/loongarch/loongarch-opts.cc: Likewise.
	* config/loongarch/loongarch-opts.h (TARGET_64BIT): Likewise.
	(ISA_BASE_IS_LA64V110): Likewise.
	* config/loongarch/loongarch-str.h (STR_ISA_BASE_LA64V110): Likewise.
	* config/loongarch/loongarch.opt: Regenerate.

diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings
index b2070c83ed004af535fdc1c0718c839fc10d9a11..7bc4824007e23b9b2a8bec0a26f290f689ff9ddf 100644 (file)
--- a/gcc/config/loongarch/genopts/loongarch-strings
+++ b/gcc/config/loongarch/genopts/loongarch-strings
@@ -30,7 +30,6 @@ STR_CPU_LA664       la664
 
 # Base architecture
 STR_ISA_BASE_LA64V100 la64
-STR_ISA_BASE_LA64V110 la64v1.1
 
 # -mfpu
 OPTSTR_ISA_EXT_FPU    fpu

diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
index 8af6cc6f532e7ec8a00a1eae5d5436c51875b9b7..483b185b059bd0b8fe758d474f27842440a5ec31 100644 (file)
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -32,9 +32,6 @@ Basic ISAs of LoongArch:
 EnumValue
 Enum(isa_base) String(@@STR_ISA_BASE_LA64V100@@) Value(ISA_BASE_LA64V100)
 
-EnumValue
-Enum(isa_base) String(@@STR_ISA_BASE_LA64V110@@) Value(ISA_BASE_LA64V110)
-
 ;; ISA extensions / adjustments
 Enum
 Name(isa_ext_fpu) Type(int)

diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc
index 622df47916f31ba6236f21caa0a153465789ee57..4033320d0e1e742a908b47bd10a17a7936b2e7d7 100644 (file)
--- a/gcc/config/loongarch/loongarch-cpu.cc
+++ b/gcc/config/loongarch/loongarch-cpu.cc
@@ -23,7 +23,6 @@ along with GCC; see the file COPYING3.  If not see
 #include "config.h"
 #include "system.h"
 #include "coretypes.h"
-#include "tm.h"
 #include "diagnostic-core.h"
 
 #include "loongarch-def.h"
@@ -32,19 +31,6 @@ along with GCC; see the file COPYING3.  If not see
 #include "loongarch-cpucfg-map.h"
 #include "loongarch-str.h"
 
-/* loongarch_isa_base_features defined here instead of loongarch-def.c
-   because we need to use options.h.  Pay attention on the order of elements
-   in the initializer becaue ISO C++ does not allow C99 designated
-   initializers!  */
-
-#define ISA_BASE_LA64V110_FEATURES \
-  (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA \
-   | OPTION_MASK_ISA_LAM_BH | OPTION_MASK_ISA_LAMCAS)
-
-int64_t loongarch_isa_base_features[N_ISA_BASE_TYPES] = {
-  /* [ISA_BASE_LA64V100] = */ 0,
-  /* [ISA_BASE_LA64V110] = */ ISA_BASE_LA64V110_FEATURES,
-};
 
 /* Native CPU detection with "cpucfg" */
 static uint32_t cpucfg_cache[N_CPUCFG_WORDS] = { 0 };
@@ -235,18 +221,20 @@ fill_native_cpu_config (struct loongarch_target *tgt)
       /* Use the native value anyways.  */
       preset.simd = tmp;
 
+
+      int64_t hw_isa_evolution = 0;
+
       /* Features added during ISA evolution.  */
       for (const auto &entry: cpucfg_map)
        if (cpucfg_cache[entry.cpucfg_word] & entry.cpucfg_bit)
-         preset.evolution |= entry.isa_evolution_bit;
+         hw_isa_evolution |= entry.isa_evolution_bit;
 
       if (native_cpu_type != CPU_NATIVE)
        {
          /* Check if the local CPU really supports the features of the base
             ISA of probed native_cpu_type.  If any feature is not detected,
             either GCC or the hardware is buggy.  */
-         auto base_isa_feature = loongarch_isa_base_features[preset.base];
-         if ((preset.evolution & base_isa_feature) != base_isa_feature)
+         if ((preset.evolution & hw_isa_evolution) != hw_isa_evolution)
            warning (0,
                     "detected base architecture %qs, but some of its "
                     "features are not detected; the detected base "
@@ -254,6 +242,7 @@ fill_native_cpu_config (struct loongarch_target *tgt)
                     "features will be enabled",
                     loongarch_isa_base_strings[preset.base]);
        }
+      preset.evolution = hw_isa_evolution;
     }
 
   if (tune_native_p)

diff --git a/gcc/config/loongarch/loongarch-def.cc b/gcc/config/loongarch/loongarch-def.cc
index 6990c86c2c49d1d688eae1c42bbf21107ad31e3e..bc6997e45b5c11fa7a6c2b3f4d4f012168aa1237 100644 (file)
--- a/gcc/config/loongarch/loongarch-def.cc
+++ b/gcc/config/loongarch/loongarch-def.cc
@@ -18,6 +18,11 @@ You should have received a copy of the GNU General Public License
 along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+
 #include "loongarch-def.h"
 #include "loongarch-str.h"
 
@@ -51,9 +56,11 @@ array_arch<loongarch_isa> loongarch_cpu_default_isa =
            .simd_ (ISA_EXT_SIMD_LASX))
     .set (CPU_LA664,
          loongarch_isa ()
-           .base_ (ISA_BASE_LA64V110)
+           .base_ (ISA_BASE_LA64V100)
            .fpu_ (ISA_EXT_FPU64)
-           .simd_ (ISA_EXT_SIMD_LASX));
+           .simd_ (ISA_EXT_SIMD_LASX)
+           .evolution_ (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA
+                   | OPTION_MASK_ISA_LAM_BH | OPTION_MASK_ISA_LAMCAS));
 
 static inline loongarch_cache la464_cache ()
 {
@@ -136,8 +143,7 @@ array_tune<int> loongarch_cpu_multipass_dfa_lookahead = array_tune<int> ()
 
 array<const char *, N_ISA_BASE_TYPES> loongarch_isa_base_strings =
   array<const char *, N_ISA_BASE_TYPES> ()
-    .set (ISA_BASE_LA64V100, STR_ISA_BASE_LA64V100)
-    .set (ISA_BASE_LA64V110, STR_ISA_BASE_LA64V110);
+    .set (ISA_BASE_LA64V100, STR_ISA_BASE_LA64V100);
 
 array<const char *, N_ISA_EXT_TYPES> loongarch_isa_ext_strings =
   array<const char *, N_ISA_EXT_TYPES> ()

diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index 68a9a461e54908151974f9189330bc2cdac667fa..a2c86df5bd9415e715ea9ad861ca91e917755f7a 100644 (file)
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -56,19 +56,11 @@ along with GCC; see the file COPYING3.  If not see
 /* enum isa_base */
 
 /* LoongArch V1.00.  */
-#define ISA_BASE_LA64V100     0
-/* LoongArch V1.10.  */
-#define ISA_BASE_LA64V110     1
-#define N_ISA_BASE_TYPES      2
+#define ISA_BASE_LA64V100      0
+#define N_ISA_BASE_TYPES       1
 extern loongarch_def_array<const char *, N_ISA_BASE_TYPES>
   loongarch_isa_base_strings;
 
-#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
-/* Unlike other arrays, this is defined in loongarch-cpu.cc.  The problem is
-   we cannot use the C++ header options.h in loongarch-def.c.  */
-extern int64_t loongarch_isa_base_features[];
-#endif
-
 /* enum isa_ext_* */
 #define ISA_EXT_NONE         0
 #define ISA_EXT_FPU32        1

diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc
index 7b63ef57a2a620d0ee50edf8b5ef61c7fd83360b..8689f2dab0519c1c6eaad67fde7329afd19ca9fb 100644 (file)
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -285,9 +285,6 @@ config_target_isa:
   /* Get default ISA from "-march" or its default value.  */
   t.isa = loongarch_cpu_default_isa[t.cpu_arch];
 
-  if (t.cpu_arch != CPU_NATIVE)
-    t.isa.evolution |= loongarch_isa_base_features[t.isa.base];
-
   /* Apply incremental changes.  */
   /* "-march=native" overrides the default FPU type.  */
 

diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h
index e1ec702335dea68860c5db25168b7dddec90f040..651c1c18ca8422c0cc17facab1c7b6c22fc9b239 100644 (file)
--- a/gcc/config/loongarch/loongarch-opts.h
+++ b/gcc/config/loongarch/loongarch-opts.h
@@ -77,8 +77,7 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target,
 #define TARGET_DOUBLE_FLOAT      (la_target.isa.fpu == ISA_EXT_FPU64)
 #define TARGET_DOUBLE_FLOAT_ABI          (la_target.abi.base == ABI_BASE_LP64D)
 
-#define TARGET_64BIT             (la_target.isa.base == ISA_BASE_LA64V100 \
-                                  || la_target.isa.base == ISA_BASE_LA64V110)
+#define TARGET_64BIT             (la_target.isa.base == ISA_BASE_LA64V100)
 #define TARGET_ABI_LP64                  (la_target.abi.base == ABI_BASE_LP64D \
                                   || la_target.abi.base == ABI_BASE_LP64F \
                                   || la_target.abi.base == ABI_BASE_LP64S)
@@ -90,7 +89,6 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target,
 /* TARGET_ macros for use in *.md template conditionals */
 #define TARGET_uARCH_LA464       (la_target.cpu_tune == CPU_LA464)
 #define TARGET_uARCH_LA664       (la_target.cpu_tune == CPU_LA664)
-#define ISA_BASE_IS_LA64V110     (la_target.isa.base == ISA_BASE_LA64V110)
 
 /* Note: optimize_size may vary across functions,
    while -m[no]-memcpy imposes a global constraint.  */

diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
index 0384493765c5e7b7feb5ceef37490a02fc73bdcd..7c78d1443d5f1a29457b619f9584034db4bcf8a1 100644 (file)
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -33,7 +33,6 @@ along with GCC; see the file COPYING3.  If not see
 #define STR_CPU_LA664 "la664"
 
 #define STR_ISA_BASE_LA64V100 "la64"
-#define STR_ISA_BASE_LA64V110 "la64v1.1"
 
 #define OPTSTR_ISA_EXT_FPU "fpu"
 #define STR_NONE "none"

diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index 4d36e3ec4de79049b41fbcbf04b7b5e843467e63..41e6424e8616db1a54df83cc031158eb837443c8 100644 (file)
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -40,9 +40,6 @@ Basic ISAs of LoongArch:
 EnumValue
 Enum(isa_base) String(la64) Value(ISA_BASE_LA64V100)
 
-EnumValue
-Enum(isa_base) String(la64v1.1) Value(ISA_BASE_LA64V110)
-
 ;; ISA extensions / adjustments
 Enum
 Name(isa_ext_fpu) Type(int)