message(STATUS "No optimized architecture: using ${ARCHDIR}")
endif()
if("${ARCH}" MATCHES "arm" OR "${ARCH}" MATCHES "aarch64")
- set(ZLIB_ARCH_SRCS ${ZLIB_ARCH_SRCS} ${ARCHDIR}/armfeature.c ${ARCHDIR}/fill_window_arm.c)
+ list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/armfeature.c ${ARCHDIR}/fill_window_arm.c)
endif()
if(WITH_OPTIM)
if("${ARCH}" MATCHES "arm" OR "${ARCH}" MATCHES "aarch64")
if(WITH_NEON)
- set(ZLIB_ARCH_SRCS ${ZLIB_ARCH_SRCS} ${ARCHDIR}/adler32_neon.c)
+ list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/adler32_neon.c)
add_definitions(-DARM_NEON_ADLER32)
add_intrinsics_option("${NEONFLAG}")
if(MSVC)
add_feature_info(NEON_FILLWINDOW 1 "Support NEON instructions in fill_window_arm, using \"${NEONFLAG}\"")
endif()
if(WITH_ACLE)
- set(ZLIB_ARCH_SRCS ${ZLIB_ARCH_SRCS} ${ARCHDIR}/crc32_acle.c ${ARCHDIR}/insert_string_acle.c)
+ list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/crc32_acle.c ${ARCHDIR}/insert_string_acle.c)
add_definitions(-DARM_ACLE_CRC_HASH)
# For ARM aarch64, we need to check WITH_NEON first
if("${ARCH}" MATCHES "arm" OR NOT WITH_NEON)
endif()
elseif("${ARCHDIR}" MATCHES "arch/x86")
add_definitions("-DX86_CPUID")
- set(ZLIB_ARCH_SRCS ${ZLIB_ARCH_SRCS} ${ARCHDIR}/x86.c)
+ list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/x86.c)
if(HAVE_SSE42CRC_INLINE_ASM OR HAVE_SSE42CRC_INTRIN)
add_definitions(-DX86_SSE42_CRC_HASH)
- set(ZLIB_ARCH_SRCS ${ZLIB_ARCH_SRCS} ${ARCHDIR}/insert_string_sse.c)
+ list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/insert_string_sse.c)
add_feature_info(SSE42_CRC 1 "Support CRC hash generation using the SSE4.2 instruction set, using \"${SSE4FLAG}\"")
add_intrinsics_option("${SSE4FLAG}")
if(HAVE_SSE42CRC_INTRIN)
endif()
if(WITH_NEW_STRATEGIES)
add_definitions(-DX86_QUICK_STRATEGY)
- set(ZLIB_ARCH_SRCS ${ZLIB_ARCH_SRCS} ${ARCHDIR}/deflate_quick.c)
+ list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/deflate_quick.c)
add_feature_info(SSE42_DEFLATE_QUICK 1 "Support SSE4.2-accelerated quick compression")
endif()
endif()
if(HAVE_SSE2_INTRIN)
add_definitions(-DX86_SSE2)
- set(ZLIB_ARCH_SRCS ${ZLIB_ARCH_SRCS} ${ARCHDIR}/fill_window_sse.c)
- set(ZLIB_ARCH_SRCS ${ZLIB_ARCH_SRCS} ${ARCHDIR}/slide_sse.c)
+ list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/fill_window_sse.c ${ARCHDIR}/slide_sse.c)
if(NOT ${ARCH} MATCHES "x86_64")
add_intrinsics_option("${SSE2FLAG}")
add_feature_info(FORCE_SSE2 FORCE_SSE2 "Assume CPU is SSE2 capable")
endif()
if(HAVE_PCLMULQDQ_INTRIN)
add_definitions(-DX86_PCLMULQDQ_CRC)
- set(ZLIB_ARCH_SRCS ${ZLIB_ARCH_SRCS} ${ARCHDIR}/crc_folding.c)
+ list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/crc_folding.c)
add_intrinsics_option("${PCLMULFLAG}")
if(HAVE_SSE42CRC_INLINE_ASM)
add_feature_info(PCLMUL_CRC 1 "Support CRC hash generation using PCLMULQDQ, using \"${PCLMULFLAG}\"")
endif()
elseif("${ARCH}" MATCHES "s390x")
if(WITH_DFLTCC_DEFLATE OR WITH_DFLTCC_INFLATE)
- set(ZLIB_ARCH_SRCS ${ZLIB_ARCH_SRCS} ${ARCHDIR}/dfltcc_common.c)
+ list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/dfltcc_common.c)
endif()
if(WITH_DFLTCC_DEFLATE)
add_definitions(-DS390_DFLTCC_DEFLATE)
- set(ZLIB_ARCH_SRCS ${ZLIB_ARCH_SRCS} ${ARCHDIR}/dfltcc_deflate.c)
+ list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/dfltcc_deflate.c)
endif()
if(WITH_DFLTCC_INFLATE)
add_definitions(-DS390_DFLTCC_INFLATE)
- set(ZLIB_ARCH_SRCS ${ZLIB_ARCH_SRCS} ${ARCHDIR}/dfltcc_inflate.c)
+ list(APPEND ZLIB_ARCH_SRCS ${ARCHDIR}/dfltcc_inflate.c)
endif()
endif()
endif()