arm64: dts: renesas: r9a08g045: Correct GICD and GICR sizes

[ Upstream commit ec9532628eb9d82282b8e52fd9c4a3800d87feec ]

The RZ/G3S SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB
for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU.

Despite the RZ/G3S SoC being single-core, it has two instances of GICR.

Fixes: e20396d65b959 ("arm64: dts: renesas: Add initial DTSI for RZ/G3S SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/20240730122436.350013-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index a2adc4e27ce979613f7e79f707b38f10396f12cf..17609d81af294f2fdb98e4e90abe4d2e1ba1a2bc 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -269,8 +269,8 @@
                        #interrupt-cells = <3>;
                        #address-cells = <0>;
                        interrupt-controller;
-                       reg = <0x0 0x12400000 0 0x40000>,
-                             <0x0 0x12440000 0 0x60000>;
+                       reg = <0x0 0x12400000 0 0x20000>,
+                             <0x0 0x12440000 0 0x40000>;
                        interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
                };