aarch64: TLBI Domains changes for PLBI instruction

For the PLBI instruction with optional register argument
<Rt> == 0b1111, with FEAT_TLBID enabled they are permitted to
have an Rt value which is not 0b11111 and this is allowed for
all the TLBI instructions with a <type> of ALLE1*, ALLE2* and
VMALL* and a <shareability> of IS or OS.

diff --git a/gas/testsuite/gas/aarch64/plbi-invalid-1.l b/gas/testsuite/gas/aarch64/plbi-invalid-1.l
index 3cd50dd9bbf2cd55fdc8461c1b69a7aa7e3e3a8a..9ed859a8f19defffbba5979f02fe2d1869fbe2f8 100644 (file)
--- a/gas/testsuite/gas/aarch64/plbi-invalid-1.l
+++ b/gas/testsuite/gas/aarch64/plbi-invalid-1.l
@@ -29,34 +29,34 @@
 .*: Error: missing register at operand 2 -- `plbi perme3isnxs'
 .*: Error: missing register at operand 2 -- `plbi perme3'
 .*: Error: missing register at operand 2 -- `plbi perme3nxs'
-.*: Error: extraneous register at operand 2 -- `plbi vmalle1os,x0'
-.*: Error: extraneous register at operand 2 -- `plbi vmalle1osnxs,x0'
-.*: Error: extraneous register at operand 2 -- `plbi vmalle1os,xzr'
-.*: Error: extraneous register at operand 2 -- `plbi vmalle1osnxs,xzr'
-.*: Error: extraneous register at operand 2 -- `plbi vmalle1is,x0'
-.*: Error: extraneous register at operand 2 -- `plbi vmalle1isnxs,x0'
-.*: Error: extraneous register at operand 2 -- `plbi vmalle1is,xzr'
-.*: Error: extraneous register at operand 2 -- `plbi vmalle1isnxs,xzr'
+.*: Error: selected processor does not support system register name 'vmalle1os'
+.*: Error: selected processor does not support system register name 'vmalle1osnxs'
+.*: Error: selected processor does not support system register name 'vmalle1os'
+.*: Error: selected processor does not support system register name 'vmalle1osnxs'
+.*: Error: selected processor does not support system register name 'vmalle1is'
+.*: Error: selected processor does not support system register name 'vmalle1isnxs'
+.*: Error: selected processor does not support system register name 'vmalle1is'
+.*: Error: selected processor does not support system register name 'vmalle1isnxs'
 .*: Error: extraneous register at operand 2 -- `plbi vmalle1,x0'
 .*: Error: extraneous register at operand 2 -- `plbi vmalle1nxs,x0'
 .*: Error: extraneous register at operand 2 -- `plbi vmalle1,xzr'
 .*: Error: extraneous register at operand 2 -- `plbi vmalle1nxs,xzr'
-.*: Error: extraneous register at operand 2 -- `plbi alle2os,x0'
-.*: Error: extraneous register at operand 2 -- `plbi alle2osnxs,x0'
-.*: Error: extraneous register at operand 2 -- `plbi alle2os,xzr'
-.*: Error: extraneous register at operand 2 -- `plbi alle2osnxs,xzr'
-.*: Error: extraneous register at operand 2 -- `plbi alle1os,x0'
-.*: Error: extraneous register at operand 2 -- `plbi alle1osnxs,x0'
-.*: Error: extraneous register at operand 2 -- `plbi alle1os,xzr'
-.*: Error: extraneous register at operand 2 -- `plbi alle1osnxs,xzr'
-.*: Error: extraneous register at operand 2 -- `plbi alle2is,x0'
-.*: Error: extraneous register at operand 2 -- `plbi alle2isnxs,x0'
-.*: Error: extraneous register at operand 2 -- `plbi alle2is,xzr'
-.*: Error: extraneous register at operand 2 -- `plbi alle2isnxs,xzr'
-.*: Error: extraneous register at operand 2 -- `plbi alle1is,x0'
-.*: Error: extraneous register at operand 2 -- `plbi alle1isnxs,x0'
-.*: Error: extraneous register at operand 2 -- `plbi alle1is,xzr'
-.*: Error: extraneous register at operand 2 -- `plbi alle1isnxs,xzr'
+.*: Error: selected processor does not support system register name 'alle2os'
+.*: Error: selected processor does not support system register name 'alle2osnxs'
+.*: Error: selected processor does not support system register name 'alle2os'
+.*: Error: selected processor does not support system register name 'alle2osnxs'
+.*: Error: selected processor does not support system register name 'alle1os'
+.*: Error: selected processor does not support system register name 'alle1osnxs'
+.*: Error: selected processor does not support system register name 'alle1os'
+.*: Error: selected processor does not support system register name 'alle1osnxs'
+.*: Error: selected processor does not support system register name 'alle2is'
+.*: Error: selected processor does not support system register name 'alle2isnxs'
+.*: Error: selected processor does not support system register name 'alle2is'
+.*: Error: selected processor does not support system register name 'alle2isnxs'
+.*: Error: selected processor does not support system register name 'alle1is'
+.*: Error: selected processor does not support system register name 'alle1isnxs'
+.*: Error: selected processor does not support system register name 'alle1is'
+.*: Error: selected processor does not support system register name 'alle1isnxs'
 .*: Error: extraneous register at operand 2 -- `plbi alle2,x0'
 .*: Error: extraneous register at operand 2 -- `plbi alle2nxs,x0'
 .*: Error: extraneous register at operand 2 -- `plbi alle2,xzr'

diff --git a/gas/testsuite/gas/aarch64/tlbid-3.d b/gas/testsuite/gas/aarch64/tlbid-3.d
new file mode 100644 (file)
index 0000000..559cbb2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbid-3.d
@@ -0,0 +1,20 @@
+#as: -march=armv9.4-a+poe2+tlbid
+#objdump: -dr
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*:    d508a100        plbi    vmalle1os, x0
+.*:    d508a900        plbi    vmalle1osnxs, x0
+.*:    d508a300        plbi    vmalle1is, x0
+.*:    d508ab00        plbi    vmalle1isnxs, x0
+.*:    d50ca100        plbi    alle2os, x0
+.*:    d50ca900        plbi    alle2osnxs, x0
+.*:    d50ca180        plbi    alle1os, x0
+.*:    d50ca980        plbi    alle1osnxs, x0
+.*:    d50ca300        plbi    alle2is, x0
+.*:    d50cab00        plbi    alle2isnxs, x0
+.*:    d50ca380        plbi    alle1is, x0
+.*:    d50cab80        plbi    alle1isnxs, x0

diff --git a/gas/testsuite/gas/aarch64/tlbid-3.s b/gas/testsuite/gas/aarch64/tlbid-3.s
new file mode 100644 (file)
index 0000000..ee69ba5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbid-3.s
@@ -0,0 +1,12 @@
+plbi   vmalle1os, x0
+plbi   vmalle1osnxs, x0
+plbi   vmalle1is, x0
+plbi   vmalle1isnxs, x0
+plbi   alle2os, x0
+plbi   alle2osnxs, x0
+plbi   alle1os, x0
+plbi   alle1osnxs, x0
+plbi   alle2is, x0
+plbi   alle2isnxs, x0
+plbi   alle1is, x0
+plbi   alle1isnxs, x0

diff --git a/gas/testsuite/gas/aarch64/tlbid-invalid-4.d b/gas/testsuite/gas/aarch64/tlbid-invalid-4.d
new file mode 100644 (file)
index 0000000..f7b0e35
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbid-invalid-4.d
@@ -0,0 +1,4 @@
+#name: Test plbi instruction without +tlbid
+#source: tlbid-3.s
+#as: -march=armv9.4-a+poe2
+#error_output: tlbid-invalid-4.l

diff --git a/gas/testsuite/gas/aarch64/tlbid-invalid-4.l b/gas/testsuite/gas/aarch64/tlbid-invalid-4.l
new file mode 100644 (file)
index 0000000..fa7470c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbid-invalid-4.l
@@ -0,0 +1,13 @@
+.*: Assembler messages:
+.*: Error: selected processor does not support system register name 'vmalle1os'
+.*: Error: selected processor does not support system register name 'vmalle1osnxs'
+.*: Error: selected processor does not support system register name 'vmalle1is'
+.*: Error: selected processor does not support system register name 'vmalle1isnxs'
+.*: Error: selected processor does not support system register name 'alle2os'
+.*: Error: selected processor does not support system register name 'alle2osnxs'
+.*: Error: selected processor does not support system register name 'alle1os'
+.*: Error: selected processor does not support system register name 'alle1osnxs'
+.*: Error: selected processor does not support system register name 'alle2is'
+.*: Error: selected processor does not support system register name 'alle2isnxs'
+.*: Error: selected processor does not support system register name 'alle1is'
+.*: Error: selected processor does not support system register name 'alle1isnxs'

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 89a4f778c32f676bc59ab92eb95892e755d70974..a50b8fd0fb81396919c26efcbac8fb6e64f39f74 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -5519,37 +5519,46 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
 
 const aarch64_sys_ins_reg aarch64_sys_regs_plbi[] =
 {
-    #define PLBI_XS_OP(OP, CODE, FLAGS) \
+#define PLBI_XS_OP(OP, CODE, FLAGS) \
+    { OP, CODE, FLAGS, AARCH64_FEATURES (2, TLBID, POE2) }, \
+    { OP "nxs", CODE | CPENS (0, 0, C8, 0), FLAGS, AARCH64_FEATURES (3, TLBID, XS, POE2) },
+
+    PLBI_XS_OP ( "alle1is",    CPENS (4, C10, C3, 4),  F_TLBID_XT)
+    PLBI_XS_OP ( "alle1os",    CPENS (4, C10, C1, 4),  F_TLBID_XT)
+    PLBI_XS_OP ( "alle2is",    CPENS (4, C10, C3, 0),  F_TLBID_XT)
+    PLBI_XS_OP ( "alle2os",    CPENS (4, C10, C1, 0),  F_TLBID_XT)
+    PLBI_XS_OP ( "vmalle1is",  CPENS (0, C10, C3, 0),  F_TLBID_XT)
+    PLBI_XS_OP ( "vmalle1os",  CPENS (0, C10, C1, 0),  F_TLBID_XT)
+
+#undef PLBI_XS_OP
+
+#define PLBI_XS_OP(OP, CODE, FLAGS) \
     { OP, CODE, FLAGS, AARCH64_FEATURE (POE2) }, \
     { OP "nxs", CODE | CPENS (0, 0, C8, 0), FLAGS, AARCH64_FEATURES (2, POE2, XS) },
 
-    PLBI_XS_OP ( "alle1",      CPENS (4, C10, C7, 4),  0 )
-    PLBI_XS_OP ( "alle1is",    CPENS (4, C10, C3, 4),  0 )
-    PLBI_XS_OP ( "alle1os",    CPENS (4, C10, C1, 4),  0 )
-    PLBI_XS_OP ( "alle2",      CPENS (4, C10, C7, 0),  0 )
-    PLBI_XS_OP ( "alle2is",    CPENS (4, C10, C3, 0),  0 )
-    PLBI_XS_OP ( "alle2os",    CPENS (4, C10, C1, 0),  0 )
-    PLBI_XS_OP ( "alle3",      CPENS (6, C10, C7, 0),  0 )
-    PLBI_XS_OP ( "alle3is",    CPENS (6, C10, C3, 0),  0 )
-    PLBI_XS_OP ( "alle3os",    CPENS (6, C10, C1, 0),  0 )
-    PLBI_XS_OP ( "aside1",     CPENS (0, C10, C7, 2),  F_HASXT )
-    PLBI_XS_OP ( "aside1is",   CPENS (0, C10, C3, 2),  F_HASXT )
-    PLBI_XS_OP ( "aside1os",   CPENS (0, C10, C1, 2),  F_HASXT )
-    PLBI_XS_OP ( "permae1",    CPENS (0, C10, C7, 3),  F_HASXT )
-    PLBI_XS_OP ( "permae1is",  CPENS (0, C10, C3, 3),  F_HASXT )
-    PLBI_XS_OP ( "permae1os",  CPENS (0, C10, C1, 3),  F_HASXT )
-    PLBI_XS_OP ( "perme1",     CPENS (0, C10, C7, 1),  F_HASXT )
-    PLBI_XS_OP ( "perme1is",   CPENS (0, C10, C3, 1),  F_HASXT )
-    PLBI_XS_OP ( "perme1os",   CPENS (0, C10, C1, 1),  F_HASXT )
-    PLBI_XS_OP ( "perme2",     CPENS (4, C10, C7, 1),  F_HASXT )
-    PLBI_XS_OP ( "perme2is",   CPENS (4, C10, C3, 1),  F_HASXT )
-    PLBI_XS_OP ( "perme2os",   CPENS (4, C10, C1, 1),  F_HASXT )
-    PLBI_XS_OP ( "perme3",     CPENS (6, C10, C7, 1),  F_HASXT )
-    PLBI_XS_OP ( "perme3is",   CPENS (6, C10, C3, 1),  F_HASXT )
-    PLBI_XS_OP ( "perme3os",   CPENS (6, C10, C1, 1),  F_HASXT )
-    PLBI_XS_OP ( "vmalle1",    CPENS (0, C10, C7, 0),  0 )
-    PLBI_XS_OP ( "vmalle1is",  CPENS (0, C10, C3, 0),  0 )
-    PLBI_XS_OP ( "vmalle1os",  CPENS (0, C10, C1, 0),  0 )
+    PLBI_XS_OP ( "alle1",      CPENS (4, C10, C7, 4),  0 )
+    PLBI_XS_OP ( "alle2",      CPENS (4, C10, C7, 0),  0 )
+    PLBI_XS_OP ( "alle3",      CPENS (6, C10, C7, 0),  0 )
+    PLBI_XS_OP ( "alle3is",    CPENS (6, C10, C3, 0),  0 )
+    PLBI_XS_OP ( "alle3os",    CPENS (6, C10, C1, 0),  0 )
+    PLBI_XS_OP ( "aside1",     CPENS (0, C10, C7, 2),  F_HASXT )
+    PLBI_XS_OP ( "aside1is",   CPENS (0, C10, C3, 2),  F_HASXT )
+    PLBI_XS_OP ( "aside1os",   CPENS (0, C10, C1, 2),  F_HASXT )
+    PLBI_XS_OP ( "permae1",    CPENS (0, C10, C7, 3),  F_HASXT )
+    PLBI_XS_OP ( "permae1is",  CPENS (0, C10, C3, 3),  F_HASXT )
+    PLBI_XS_OP ( "permae1os",  CPENS (0, C10, C1, 3),  F_HASXT )
+    PLBI_XS_OP ( "perme1",     CPENS (0, C10, C7, 1),  F_HASXT )
+    PLBI_XS_OP ( "perme1is",   CPENS (0, C10, C3, 1),  F_HASXT )
+    PLBI_XS_OP ( "perme1os",   CPENS (0, C10, C1, 1),  F_HASXT )
+    PLBI_XS_OP ( "perme2",     CPENS (4, C10, C7, 1),  F_HASXT )
+    PLBI_XS_OP ( "perme2is",   CPENS (4, C10, C3, 1),  F_HASXT )
+    PLBI_XS_OP ( "perme2os",   CPENS (4, C10, C1, 1),  F_HASXT )
+    PLBI_XS_OP ( "perme3",     CPENS (6, C10, C7, 1),  F_HASXT )
+    PLBI_XS_OP ( "perme3is",   CPENS (6, C10, C3, 1),  F_HASXT )
+    PLBI_XS_OP ( "perme3os",   CPENS (6, C10, C1, 1),  F_HASXT )
+    PLBI_XS_OP ( "vmalle1",    CPENS (0, C10, C7, 0),  0 )
+
+#undef PLBI_XS_OP
 
     { 0,       CPENS (0,0,0,0), 0, AARCH64_NO_FEATURES }
 };