mediatek: update pinconf for GL.iNet eMMC boards

Update the pin-configuration as well as maximum frequency for the eMMC
flash.

 - Use 26 MHz as the maximum clock of the eMMC memory
 - Configure 12mA as the pin drive-strength
 - Enable internal pull-reistors

Signed-off-by: Yin Ni <yin.ni@gl-inet.com>
[adapt commit message]
Signed-off-by: David Bauer <mail@david-bauer.net>

diff --git a/target/linux/mediatek/dts/mt7981a-glinet-gl-x3000-xe3000-common.dtsi b/target/linux/mediatek/dts/mt7981a-glinet-gl-x3000-xe3000-common.dtsi
index b475775b36acdcf7f92786ad6aa55d9c03ce47a5..11dd1a9edc880e0604fc902370193cc986dc1740 100644 (file)
--- a/target/linux/mediatek/dts/mt7981a-glinet-gl-x3000-xe3000-common.dtsi
+++ b/target/linux/mediatek/dts/mt7981a-glinet-gl-x3000-xe3000-common.dtsi
@@ -133,7 +133,7 @@
        pinctrl-0 = <&mmc0_pins_default>;
        pinctrl-1 = <&mmc0_pins_uhs>;
        bus-width = <8>;
-       max-frequency = <52000000>;
+       max-frequency = <26000000>;
        cap-mmc-highspeed;
        vmmc-supply = <&reg_3p3v>;
        non-removable;
@@ -217,12 +217,38 @@
                        function = "flash";
                        groups = "emmc_8";
                };
+               conf-cmd-dat {
+                       pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
+                               "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
+                               "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
+                       input-enable;
+                       drive-strength = <MTK_DRIVE_12mA>;
+                       mediatek,pull-up-adv = <1>;
+               };
+               conf-clk {
+                       pins = "SPI1_CS";
+                       drive-strength = <MTK_DRIVE_12mA>;
+                       mediatek,pull-down-adv = <2>;
+               };
        };
        mmc0_pins_uhs: mmc0-pins-uhs {
                mux {
                        function = "flash";
                        groups = "emmc_8";
                };
+               conf-cmd-dat {
+                       pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
+                               "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
+                               "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
+                       input-enable;
+                       drive-strength = <MTK_DRIVE_12mA>;
+                       mediatek,pull-up-adv = <1>;
+               };
+               conf-clk {
+                       pins = "SPI1_CS";
+                       drive-strength = <MTK_DRIVE_12mA>;
+                       mediatek,pull-down-adv = <2>;
+               };
        };
        pcie_pins: pcie-pins {
                mux {

diff --git a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dtsi b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dtsi
index 1132ef80f45ab844783c50aa12d9b990e5137ae5..82cb938058a661427c85f7702c813296cb434c4a 100644 (file)
--- a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dtsi
+++ b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dtsi
@@ -78,12 +78,38 @@
                        function = "flash";
                        groups = "emmc_45";
                };
+               conf-cmd-dat {
+                       pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
+                               "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
+                               "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
+                       input-enable;
+                       drive-strength = <MTK_DRIVE_12mA>;
+                       mediatek,pull-up-adv = <1>;
+               };
+               conf-clk {
+                       pins = "SPI1_CS";
+                       drive-strength = <MTK_DRIVE_12mA>;
+                       mediatek,pull-down-adv = <2>;
+               };
        };
        mmc0_pins_uhs: mmc0-pins-uhs {
                mux {
                        function = "flash";
                        groups = "emmc_45";
                };
+               conf-cmd-dat {
+                       pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
+                               "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
+                               "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
+                       input-enable;
+                       drive-strength = <MTK_DRIVE_12mA>;
+                       mediatek,pull-up-adv = <1>;
+               };
+               conf-clk {
+                       pins = "SPI1_CS";
+                       drive-strength = <MTK_DRIVE_12mA>;
+                       mediatek,pull-down-adv = <2>;
+               };
        };
 };
 
@@ -144,7 +170,7 @@
        pinctrl-0 = <&mmc0_pins_default>;
        pinctrl-1 = <&mmc0_pins_uhs>;
        bus-width = <8>;
-       max-frequency = <52000000>;
+       max-frequency = <26000000>;
        vmmc-supply = <&reg_3p3v>;
        cap-mmc-highspeed;
        non-removable;