arm64: mm: When logging data aborts only decode Xs when ISV=1

When logging the decode of a data abort we currently unconditionally decode
and display Xs. Currently the only defined non-RES0 values for this field
are for cases where ISV=1, move the decode of Xs into our existing check
for ISV=1. This avoids potential confusion if some other use is assigned to
these bits for ISV=0 cases in future, or misleading someone into thinking
there is a meaningful value there with currently defined architecture.

Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 85e23388f9bb0c96e94a7f709090591141a389a6..0b52557652be66a5190b0a152a5e47d4dec07f06 100644 (file)
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -76,6 +76,8 @@ static void data_abort_decode(unsigned long esr)
                pr_alert("  SF = %lu, AR = %lu\n",
                         (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT,
                         (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT);
+               pr_alert("  Xs = %llu\n",
+                        (iss2 & ESR_ELx_Xs_MASK) >> ESR_ELx_Xs_SHIFT);
        } else {
                pr_alert("  ISV = 0, ISS = 0x%08lx, ISS2 = 0x%08lx\n",
                         esr & ESR_ELx_ISS_MASK, iss2);
@@ -87,11 +89,10 @@ static void data_abort_decode(unsigned long esr)
                 (iss2 & ESR_ELx_TnD) >> ESR_ELx_TnD_SHIFT,
                 (iss2 & ESR_ELx_TagAccess) >> ESR_ELx_TagAccess_SHIFT);
 
-       pr_alert("  GCS = %ld, Overlay = %lu, DirtyBit = %lu, Xs = %llu\n",
+       pr_alert("  GCS = %ld, Overlay = %lu, DirtyBit = %lu\n",
                 (iss2 & ESR_ELx_GCS) >> ESR_ELx_GCS_SHIFT,
                 (iss2 & ESR_ELx_Overlay) >> ESR_ELx_Overlay_SHIFT,
-                (iss2 & ESR_ELx_DirtyBit) >> ESR_ELx_DirtyBit_SHIFT,
-                (iss2 & ESR_ELx_Xs_MASK) >> ESR_ELx_Xs_SHIFT);
+                (iss2 & ESR_ELx_DirtyBit) >> ESR_ELx_DirtyBit_SHIFT);
 }
 
 static void mem_abort_decode(unsigned long esr)