arm64: dts: imx8mm-tqma8mqml: fix LDO5 power off

Fix SD card removal caused by automatic LDO5 power off after boot.

To prevent this, add vqmmc regulator for USDHC, using a GPIO-controlled
regulator that is supplied by LDO5. Since this is implemented on SoM but
used on baseboards with SD-card interface, implement the functionality
on SoM part and optionally enable it on baseboards if needed.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
index b941c8c4f7bb44a02fe1f6587050aeb517435b19..8dcc5cbcb8f66204dead0f71e42a7350c3cd3b86 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
@@ -101,6 +101,10 @@
        status = "okay";
 };
 
+&reg_usdhc2_vqmmc {
+       status = "okay";
+};
+
 &sai3 {
        assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
        assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
@@ -276,8 +280,7 @@
                           <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0         0x1d4>,
                           <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1         0x1d4>,
                           <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2         0x1d4>,
-                          <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>,
-                          <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0x84>;
+                          <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>;
        };
 
        pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
@@ -286,8 +289,7 @@
                           <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0         0x1d4>,
                           <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1         0x1d4>,
                           <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2         0x1d4>,
-                          <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>,
-                          <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0x84>;
+                          <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>;
        };
 
        pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
@@ -296,7 +298,6 @@
                           <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0         0x1d4>,
                           <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1         0x1d4>,
                           <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2         0x1d4>,
-                          <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>,
-                          <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0x84>;
+                          <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>;
        };
 };

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi
index 2e3860a5f4fd2be66897487b4dbe04c1890c32da..29b298af0d739100d33ff43a8b955a37821b3ef7 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi
@@ -16,6 +16,20 @@
                reg = <0x00000000 0x40000000 0 0x40000000>;
        };
 
+       reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
+               compatible = "regulator-gpio";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>;
+               regulator-name = "V_SD2";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+               gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+               states = <1800000 0x1>,
+                        <3300000 0x0>;
+               vin-supply = <&ldo5_reg>;
+               status = "disabled";
+       };
+
        reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -227,6 +241,10 @@
        fsl,clkreq-unsupported;
 };
 
+&usdhc2 {
+       vqmmc-supply = <&reg_usdhc2_vqmmc>;
+};
+
 &usdhc3 {
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc3>;
@@ -281,6 +299,10 @@
                fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19         0x84>;
        };
 
+       pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp {
+               fsl,pins = <MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4           0xc0>;
+       };
+
        pinctrl_usdhc3: usdhc3grp {
                fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK           0x1d4>,
                           <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD           0x1d2>,