}
-const u8 ALIGN_AVX_DIRECTIVE p_mask_interleave[64] = {
+const u8 ALIGN_CL_DIRECTIVE p_mask_interleave[64] = {
0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55,
for (auto v : sheng_states) {
dstate_id_t s = g[v].index;
if (contains(accel_escape_info, s)) {
- assert(!info.states[s].impl_id);
+ if (info.states[s].impl_id == 0) {
+ DEBUG_PRINTF("impl_id == 0!\n");
+ }
info.states[s].impl_id = sheng_end++;
info.extra[s].sheng_id = info.states[s].impl_id - 1;
}
// Dump the contents of the given queue.
static never_inline UNUSED
void debugQueue(const struct mq *q) {
+#ifdef __cplusplus
if (q == nullptr) {
+#else
+ if (q == NULL) {
+#endif
DEBUG_PRINTF("q=NULL!\n");
return;
}
if (v == succr) {
continue;
}
- DEBUG_PRINTF("Node %zu depth %u\n", g[succ].index, d + 1);
+ DEBUG_PRINTF("Node %zu depth %u\n", g[succr].index, d + 1);
next.insert(succr);
}
}
if (v == predc) {
continue;
}
- DEBUG_PRINTF("Node %zu depth %u\n", g[pred].index, d + 1);
+ DEBUG_PRINTF("Node %zu depth %u\n", g[predc].index, d + 1);
next.insert(predc);
}
}
u32 lit_id = lit_offset.first;
u32 offset = lit_offset.second;
- DEBUG_PRINTF("hash 0x%08x lit_id %u offset %u bucket %u\n", hash,
- lit_id, offset, bucket);
+ DEBUG_PRINTF("hash 0x%08x lit_id %u offset %u bucket %u\n", m.first, lit_id, offset, bucket);
auto &entry = tab[bucket];
entry.str_offset = verify_u32(litToOffsetVal.at(lit_id));
// perusal.
static UNUSED
void dumpData(const char *data, size_t len) {
+ if (!data) return;
DEBUG_PRINTF("BUFFER:");
for (size_t i = 0; i < len; i++) {
u8 c = data[i];
static inline void init_nfa(struct NFA **out_nfa, sheng_compile_ptr compile_function, init_raw_dfa_ptr init_dfa_function) {
ue2::Grey *g = new ue2::Grey();
+#if defined(HAVE_AVX512VBMI)
+ hs_platform_info plat_info = {0, HS_CPU_FEATURES_AVX512VBMI, 0, 0};
+#else
hs_platform_info plat_info = {0, 0, 0, 0};
+#endif
ue2::CompileContext *cc = new ue2::CompileContext(false, false, ue2::target_t(plat_info), *g);
ue2::ReportManager *rm = new ue2::ReportManager(*g);
ue2::Report *report = new ue2::Report(ue2::EXTERNAL_CALLBACK, 0);
}
#endif
ue2::Grey *g = new ue2::Grey();
- hs_platform_info plat_info = {0, 0, 0, 0};
+ hs_platform_info plat_info = {0, HS_CPU_FEATURES_AVX512VBMI, 0, 0};
ue2::CompileContext *cc = new ue2::CompileContext(false, false, ue2::target_t(plat_info), *g);
ue2::ReportManager *rm = new ue2::ReportManager(*g);
ue2::Report *report = new ue2::Report(ue2::EXTERNAL_CALLBACK, 0);
}
#endif /* defined(HAVE_AVX512VBMI) || defined(HAVE_SVE) */
-} /* namespace */
\ No newline at end of file
+} /* namespace */