static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
- int x, int y, int atomic)
+ int x, int y)
{
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct drm_device *dev = crtc->dev;
bool bypass_lut = false;
/* no fb bound */
- if (!atomic && !crtc->primary->fb) {
+ if (!crtc->primary->fb) {
DRM_DEBUG_KMS("No FB bound\n");
return 0;
}
- if (atomic)
- target_fb = fb;
- else
- target_fb = crtc->primary->fb;
+ target_fb = crtc->primary->fb;
/* If atomic, assume fb object is pinned & idle & fenced and
* just update base pointers
if (unlikely(r != 0))
return r;
- if (!atomic) {
- abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
- r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
- if (unlikely(r != 0)) {
- amdgpu_bo_unreserve(abo);
- return -EINVAL;
- }
+ abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+ r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
+ if (unlikely(r != 0)) {
+ amdgpu_bo_unreserve(abo);
+ return -EINVAL;
}
fb_location = amdgpu_bo_gpu_offset(abo);
/* set pageflip to happen anywhere in vblank interval */
WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
- if (!atomic && fb && fb != crtc->primary->fb) {
+ if (fb && fb != crtc->primary->fb) {
abo = gem_to_amdgpu_bo(fb->obj[0]);
r = amdgpu_bo_reserve(abo, true);
if (unlikely(r != 0))
amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
- dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
+ dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y);
amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
amdgpu_atombios_crtc_scaler_setup(crtc);
dce_v10_0_cursor_reset(crtc);
static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
struct drm_framebuffer *old_fb)
{
- return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
-}
-
-static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
- struct drm_framebuffer *fb,
- int x, int y, enum mode_set_atomic state)
-{
- return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
+ return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y);
}
static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
.mode_fixup = dce_v10_0_crtc_mode_fixup,
.mode_set = dce_v10_0_crtc_mode_set,
.mode_set_base = dce_v10_0_crtc_set_base,
- .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
.prepare = dce_v10_0_crtc_prepare,
.commit = dce_v10_0_crtc_commit,
.disable = dce_v10_0_crtc_disable,
static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
- int x, int y, int atomic)
+ int x, int y)
{
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct drm_device *dev = crtc->dev;
bool bypass_lut = false;
/* no fb bound */
- if (!atomic && !crtc->primary->fb) {
+ if (!crtc->primary->fb) {
DRM_DEBUG_KMS("No FB bound\n");
return 0;
}
- if (atomic)
- target_fb = fb;
- else
- target_fb = crtc->primary->fb;
+ target_fb = crtc->primary->fb;
/* If atomic, assume fb object is pinned & idle & fenced and
* just update base pointers
if (unlikely(r != 0))
return r;
- if (!atomic) {
- abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
- r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
- if (unlikely(r != 0)) {
- amdgpu_bo_unreserve(abo);
- return -EINVAL;
- }
+ abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+ r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
+ if (unlikely(r != 0)) {
+ amdgpu_bo_unreserve(abo);
+ return -EINVAL;
}
fb_location = amdgpu_bo_gpu_offset(abo);
/* set pageflip to happen anywhere in vblank interval */
WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
- if (!atomic && fb && fb != crtc->primary->fb) {
+ if (fb && fb != crtc->primary->fb) {
abo = gem_to_amdgpu_bo(fb->obj[0]);
r = amdgpu_bo_reserve(abo, true);
if (unlikely(r != 0))
amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
- dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
+ dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y);
amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
amdgpu_atombios_crtc_scaler_setup(crtc);
dce_v6_0_cursor_reset(crtc);
static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
struct drm_framebuffer *old_fb)
{
- return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
-}
-
-static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc,
- struct drm_framebuffer *fb,
- int x, int y, enum mode_set_atomic state)
-{
- return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1);
+ return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y);
}
static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = {
.mode_fixup = dce_v6_0_crtc_mode_fixup,
.mode_set = dce_v6_0_crtc_mode_set,
.mode_set_base = dce_v6_0_crtc_set_base,
- .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic,
.prepare = dce_v6_0_crtc_prepare,
.commit = dce_v6_0_crtc_commit,
.disable = dce_v6_0_crtc_disable,
static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
- int x, int y, int atomic)
+ int x, int y)
{
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct drm_device *dev = crtc->dev;
bool bypass_lut = false;
/* no fb bound */
- if (!atomic && !crtc->primary->fb) {
+ if (!crtc->primary->fb) {
DRM_DEBUG_KMS("No FB bound\n");
return 0;
}
- if (atomic)
- target_fb = fb;
- else
- target_fb = crtc->primary->fb;
+ target_fb = crtc->primary->fb;
/* If atomic, assume fb object is pinned & idle & fenced and
* just update base pointers
if (unlikely(r != 0))
return r;
- if (!atomic) {
- abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
- r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
- if (unlikely(r != 0)) {
- amdgpu_bo_unreserve(abo);
- return -EINVAL;
- }
+ abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+ r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
+ if (unlikely(r != 0)) {
+ amdgpu_bo_unreserve(abo);
+ return -EINVAL;
}
fb_location = amdgpu_bo_gpu_offset(abo);
/* set pageflip to happen anywhere in vblank interval */
WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
- if (!atomic && fb && fb != crtc->primary->fb) {
+ if (fb && fb != crtc->primary->fb) {
abo = gem_to_amdgpu_bo(fb->obj[0]);
r = amdgpu_bo_reserve(abo, true);
if (unlikely(r != 0))
amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
- dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
+ dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y);
amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
amdgpu_atombios_crtc_scaler_setup(crtc);
dce_v8_0_cursor_reset(crtc);
static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
struct drm_framebuffer *old_fb)
{
- return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
-}
-
-static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
- struct drm_framebuffer *fb,
- int x, int y, enum mode_set_atomic state)
-{
- return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
+ return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y);
}
static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
.mode_fixup = dce_v8_0_crtc_mode_fixup,
.mode_set = dce_v8_0_crtc_mode_set,
.mode_set_base = dce_v8_0_crtc_set_base,
- .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
.prepare = dce_v8_0_crtc_prepare,
.commit = dce_v8_0_crtc_commit,
.disable = dce_v8_0_crtc_disable,