unsigned int integer_bits,
unsigned int fractional_bits)
{
+ (void)integer_bits;
struct fixed31_32 fixpt_value = dc_fixpt_from_int(int_value);
fixpt_value.value |= (long long)frac_value << (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits);
void *initial_value,
uint32_t struct_size)
{
+ (void)ctx;
uint32_t i;
vector->container = NULL;
struct slot_layout_info *slot_layout_info,
unsigned int record_offset)
{
+ (void)i;
unsigned int j;
struct bios_parser *bp;
ATOM_BRACKET_LAYOUT_RECORD *record;
struct graphics_object_id object_id, uint32_t index,
struct graphics_object_id *src_object_id)
{
+ (void)index;
struct bios_parser *bp = BP_FROM_DCB(dcb);
unsigned int i;
enum bp_result bp_result = BP_RESULT_BADINPUT;
uint32_t device_tag_index,
struct connector_device_tag_info *info)
{
+ (void)device_tag_index;
struct bios_parser *bp = BP_FROM_DCB(dcb);
struct atom_display_object_path_v2 *object;
uint32_t index,
struct spread_spectrum_info *ss_info)
{
+ (void)index;
enum bp_result result = BP_RESULT_OK;
struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
struct atom_smu_info_v3_3 *smu_info = NULL;
uint32_t index,
struct spread_spectrum_info *ss_info)
{
+ (void)index;
enum bp_result result = BP_RESULT_OK;
struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
struct atom_smu_info_v3_1 *smu_info = NULL;
uint32_t index,
struct spread_spectrum_info *ss_info)
{
+ (void)index;
enum bp_result result = BP_RESULT_OK;
struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
struct dc_bios *dcb,
enum as_signal_type signal)
{
+ (void)dcb;
+ (void)signal;
/* TODO: DAL2 atomfirmware implementation does not need this.
* why DAL3 need this?
*/
struct dc_bios *dcb,
void *dst)
{
+ (void)dcb;
+ (void)dst;
// TODO: There is data bytes alignment issue, disable it for now.
return 0;
}
struct bios_parser *bp,
struct bp_external_encoder_control *cntl)
{
+ (void)bp;
+ (void)cntl;
/* TODO */
return BP_RESULT_OK;
}
static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
{
+ (void)id;
/* On any ASIC after DCE80, we manually program the DIG_FE
* selection (see connect_dig_be_to_fe function of the link
* encoder), so translation should always return 0 (no FE).
static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
{
+ (void)id;
/* On any ASIC after DCE80, we manually program the DIG_FE
* selection (see connect_dig_be_to_fe function of the link
* encoder), so translation should always return 0 (no FE).
static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
{
+ (void)id;
/* On any ASIC after DCE80, we manually program the DIG_FE
* selection (see connect_dig_be_to_fe function of the link
* encoder), so translation should always return 0 (no FE).
struct dc *dc,
struct dc_state *context)
{
+ (void)dc;
int i, total_plane_count;
total_plane_count = 0;
struct pp_smu_funcs *pp_smu,
struct dccg *dccg)
{
+ (void)pp_smu;
struct clk_state_registers_and_bypass s = { 0 };
clk_mgr->base.ctx = ctx;
static void dcn31_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
{
+ (void)regs_and_bypass;
+ (void)clk_mgr_base;
+ (void)log_info;
return;
}
static void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
{
+ (void)regs_and_bypass;
+ (void)clk_mgr_base;
+ (void)log_info;
return;
}
static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
{
+ (void)regs_and_bypass;
+ (void)clk_mgr_base;
+ (void)log_info;
return;
}
static void dcn316_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
{
+ (void)regs_and_bypass;
+ (void)clk_mgr_base;
+ (void)log_info;
return;
}
static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
{
+ (void)log_info;
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
uint32_t dprefclk_did = 0;
uint32_t dcfclk_did = 0;
struct pp_smu_funcs *pp_smu,
struct dccg *dccg)
{
+ (void)pp_smu;
struct clk_log_info log_info = {0};
clk_mgr->base.ctx = ctx;
static void dcn401_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
{
+ (void)log_info;
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
uint32_t dprefclk_did = 0;
uint32_t dcfclk_did = 0;
struct dc_state *context,
int ref_dtbclk_khz)
{
+ (void)ref_dtbclk_khz;
int i;
struct dccg *dccg = clk_mgr->dccg;
struct pipe_ctx *otg_master;
struct clk_mgr_internal *clk_mgr,
struct dc_state *context)
{
+ (void)context;
uint32_t new_disp_divider = 0;
uint32_t new_dispclk_wdivider = 0;
uint32_t dentist_dispclk_wdivider_readback = 0;
struct dc_state *context,
int ref_dtbclk_khz)
{
+ (void)clk_mgr;
+ (void)context;
+ (void)ref_dtbclk_khz;
/* DCN42 does not implement set_dtbclk_dto function, so this is a no-op */
}
void dcn42_exit_low_power_state(struct clk_mgr *clk_mgr_base)
{
+ (void)clk_mgr_base;
}
int dcn42_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
{
+ (void)clk_mgr_base;
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
uint32_t dispclk_wdivider;
int disp_divider;
struct dc_stream_state *stream,
struct dc_state *context)
{
+ (void)dc;
+ (void)context;
int i;
for (i = 0; i < stream->num_wb_info; i++)
struct dc_stream_state *stream,
bool lock)
{
+ (void)dc;
+ (void)context;
int i;
/* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
*/
static void force_immediate_gsl_plane_flip(struct dc *dc, struct dc_surface_update *updates, int surface_count)
{
+ (void)dc;
bool has_flip_immediate_plane = false;
int i;
struct dc_stream_state *stream,
struct dc_stream_update *update)
{
+ (void)context;
struct dc_context *dc_ctx = dc->ctx;
if (update == NULL || stream == NULL)
static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream)
{
+ (void)dc;
if ((stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1
|| stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
&& stream->ctx->dce_version >= DCN_VERSION_3_1)
int surface_count,
bool *is_plane_addition)
{
+ (void)srf_updates;
struct dc_stream_status *cur_stream_status = stream_get_status(dc->current_state, stream);
bool force_minimal_pipe_splitting = false;
struct dc_stream_update *stream_update,
struct dc_state *state)
{
+ (void)state;
bool ret = false;
dc_exit_ips_for_hw_access(dc);
static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz)
{
+ (void)apply;
struct dc_state *context = dc->current_state;
struct hubp *hubp;
struct pipe_ctx *pipe;
void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
bool powerOn)
{
+ (void)dc;
if (edp_link->connector_signal != SIGNAL_TYPE_EDP)
return;
void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst,
struct power_features *out_data)
{
+ (void)primary_otg_inst;
out_data->uclk_p_state = dc->current_state->clk_mgr->clks.p_state_change_support;
out_data->fams = dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
}
enum dc_color_space colorspace,
struct tg_color *black_color)
{
+ (void)dc;
switch (colorspace) {
case COLOR_SPACE_YCBCR601:
case COLOR_SPACE_YCBCR709:
const struct dc *dc,
struct dc_state *context)
{
+ (void)dc;
int i;
for (i = 0; i < MAX_PIPES; i++) {
struct resource_context *new_res_ctx,
const struct pipe_ctx *cur_otg_master)
{
+ (void)cur_res_ctx;
const struct pipe_ctx *cur_sec_opp_head = cur_otg_master->next_odm_pipe;
struct pipe_ctx *new_pipe;
int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
struct resource_context *new_res_ctx,
const struct pipe_ctx *cur_opp_head)
{
+ (void)cur_res_ctx;
const struct pipe_ctx *cur_sec_dpp = cur_opp_head->bottom_pipe;
struct pipe_ctx *new_pipe;
int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
const struct resource_pool *pool,
struct dc_stream_state *stream)
{
+ (void)pool;
struct dc *dc = stream->ctx->dc;
return dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
struct dc_plane_state *plane_state,
struct dc_state *context)
{
+ (void)context;
struct pipe_ctx *opp_head_pipe = otg_master_pipe;
while (opp_head_pipe) {
const struct resource_pool *pool,
struct dc_stream_state *stream)
{
+ (void)stream;
int i;
for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
enum engine_id id,
enum dce_version dc_version)
{
+ (void)dc_version;
int i, available_audio_count;
if (id == ENGINE_ID_UNKNOWN)
struct dc_state *state,
struct dc_stream_state *stream)
{
+ (void)dc;
enum dc_status res;
DC_LOGGER_INIT(dc->ctx->logger);
struct dc_state *state,
struct dc_plane_state *main_plane)
{
+ (void)main_plane;
struct dc_plane_state *phantom_plane = dc_create_plane_state(dc);
DC_LOGGER_INIT(dc->ctx->logger);
void dc_plane_destruct(struct dc_plane_state *plane_state)
{
+ (void)plane_state;
// no more pointers to free within dc_plane_state
}
struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx,
const struct hubp *hubp, const struct dpp *dpp)
{
+ (void)p_idx;
/* Hubp */
pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH;
pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR;
uint8_t shift1, uint32_t mask1, uint32_t field_value1,
va_list ap)
{
+ (void)addr;
uint32_t shift, mask, field_value;
int i = 1;
int otg_inst,
int dp_hpo_inst)
{
+ (void)dp_hpo_inst;
if (src == REFCLK)
dccg31_disable_dpstreamclk(dccg, otg_inst);
else
unsigned int xtalin_freq_inKhz,
unsigned int *dccg_ref_freq_inKhz)
{
+ (void)dccg;
/*
* Assume refclk is sourced from xtalin
* expect 24MHz
unsigned int xtalin_freq_inKhz,
unsigned int *dccg_ref_freq_inKhz)
{
+ (void)dccg;
/*
* Assume refclk is sourced from xtalin
* expect 100MHz
static int
dccg35_is_symclk32_se_src_functional_le_new(struct dccg *dccg, int symclk_32_se_inst, int symclk_32_le_inst)
{
+ (void)symclk_32_se_inst;
uint32_t en;
uint32_t src_sel;
uint32_t stream_enc_inst,
uint32_t link_enc_inst)
{
+ (void)link_enc_inst;
dccg35_disable_symclk_fe_new(dccg, stream_enc_inst);
/* DMU PHY sequence switches SYMCLK_BE (link_enc_inst) to ref clock once PHY is turned off */
enum pixel_rate_div tmds_div,
enum pixel_rate_div unused)
{
+ (void)unused;
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
uint32_t cur_tmds_div = PIXEL_RATE_DIV_NA;
uint32_t dp_dto_int;
unsigned int xtalin_freq_inKhz,
unsigned int *dccg_ref_freq_inKhz)
{
+ (void)dccg;
/*
* Assume refclk is sourced from xtalin
* expect 100MHz
void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h)
{
+ (void)num_slices_h;
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
switch (inst) {
void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)
{
+ (void)link_enc_inst;
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
switch (stream_enc_inst) {
enum pixel_rate_div tmds_div,
enum pixel_rate_div unused)
{
+ (void)unused;
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
uint32_t cur_tmds_div = PIXEL_RATE_DIV_NA;
uint32_t dp_dto_int;
static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id, uint32_t panel_inst)
{
+ (void)panel_inst;
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
uint32_t rampingBoundary = 0xFFFF;
uint32_t av_stream_map_lane_count,
uint32_t audio_sdp_overhead)
{
+ (void)channel_count;
/* DP spec recommends between 1.05 to 1.1 safety margin to prevent sample under-run */
struct fixed31_32 audio_sdp_margin = dc_fixpt_from_fraction(110, 100);
struct fixed31_32 horizontal_line_freq_khz = dc_fixpt_from_fraction(
uint32_t actual_pixel_clock_100Hz,
struct azalia_clock_info *azalia_clock_info)
{
+ (void)crtc_pixel_clock_100hz;
/* audio_dto_phase= 24 * 10,000;
* 24MHz in [100Hz] units */
azalia_clock_info->audio_dto_phase =
const struct audio_pll_info *pll_info,
struct azalia_clock_info *azalia_clock_info)
{
+ (void)requested_pixel_clock_100Hz;
/* Reported dpDtoSourceClockInkhz value for
* DCE8 already adjusted for SS, do not need any
* adjustment here anymore
struct pll_settings *pll_settings,
struct pixel_clk_params *pix_clk_params)
{
+ (void)clk_src;
uint32_t actual_pixel_clock_100hz;
actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz;
enum dp_link_encoding encoding,
struct pll_settings *pll_settings)
{
+ (void)encoding;
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
struct bp_pixel_clock_parameters bp_pc_params = {0};
enum dp_link_encoding encoding,
struct pll_settings *pll_settings)
{
+ (void)encoding;
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
struct bp_pixel_clock_parameters bp_pc_params = {0};
enum dp_link_encoding encoding,
struct pll_settings *pll_settings)
{
+ (void)encoding;
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
const struct pixel_rate_range_table_entry *e =
static bool dce_dmcu_init(struct dmcu *dmcu)
{
+ (void)dmcu;
// Do nothing
return true;
}
size_t slave_address
)
{
+ (void)pool;
struct dc *dc = ddc->ctx->dc;
struct dc_bios *dcb = dc->ctx->dc_bios;
struct graphics_object_id id = {0};
struct dce_i2c_hw *dce_i2c_hw,
uint8_t *returned_bytes)
{
+ (void)returned_bytes;
uint32_t i2c_sw_status = 0;
uint32_t value =
REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
struct i2c_command *cmd,
struct dce_i2c_hw *dce_i2c_hw)
{
+ (void)ddc;
uint8_t index_of_payload = 0;
bool result;
struct resource_pool *pool,
struct dce_i2c_sw *dce_i2c_sw)
{
+ (void)pool;
dal_ddc_close(dce_i2c_sw->ddc);
dce_i2c_sw->ddc = NULL;
}
struct ddc *ddc,
uint16_t clock_delay_div_4)
{
+ (void)ctx;
uint32_t scl_retry = 0;
uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4;
struct i2c_command *cmd,
struct dce_i2c_sw *dce_i2c_sw)
{
+ (void)ddc;
uint8_t index_of_payload = 0;
bool result;
const struct dc_cursor_position *position,
const struct dc_cursor_mi_param *param)
{
+ (void)param;
struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
/* lock cursor registers */
const struct dce110_link_encoder *enc110,
const struct dc_crtc_timing *crtc_timing)
{
+ (void)enc110;
if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
return false;
struct dce_watermarks urgent,
uint32_t total_dest_line_time_ns)
{
+ (void)stutter_enter;
struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
struct dce_watermarks urgent,
uint32_t total_dest_line_time_ns)
{
+ (void)stutter_entry;
struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror)
{
+ (void)dcc;
+ (void)horizontal_mirror;
struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);
enum dc_color_depth color_dpth,
enum signal_type signal)
{
+ (void)color_sp;
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
bool use_vsc_sdp_for_colorimetry,
uint32_t enable_sdp_splitting)
{
+ (void)use_vsc_sdp_for_colorimetry;
+ (void)enable_sdp_splitting;
uint32_t h_active_start;
uint32_t v_active_start;
uint32_t misc0 = 0;
struct dc_link *link,
struct stream_encoder *enc)
{
+ (void)link;
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
uint32_t reg1 = 0;
uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
struct stream_encoder *enc,
const struct encoder_unblank_param *param)
{
+ (void)link;
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
const struct scaler_data *data,
struct scl_ratios_inits *inits)
{
+ (void)xfm_dce;
struct fixed31_32 h_init;
struct fixed31_32 v_init;
const struct out_csc_color_matrix *tbl_entry,
enum grph_color_adjust_option options)
{
+ (void)options;
{
REG_SET_2(OUTPUT_CSC_C11_C12, 0,
OUTPUT_CSC_C11, tbl_entry->regval[0],
unsigned int controller_id,
unsigned int panel_inst)
{
+ (void)controller_id;
bool ret = false;
unsigned int feature_support;
bool dmub_abm_set_pause(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int stream_inst)
{
+ (void)stream_inst;
union dmub_rb_cmd cmd;
struct dc_context *dc = abm->ctx;
uint8_t panel_mask = 0x01 << panel_inst;
uint8_t panel_inst,
uint16_t frame_skip_number)
{
+ (void)panel_inst;
union dmub_rb_cmd cmd;
struct dc_context *dc = dmub->ctx;
struct dmub_rb_cmd_replay_set_coasting_vtotal *pCmd = NULL;
struct dce_mem_input *mem_input110,
bool immediate)
{
+ (void)immediate;
uint32_t value = 0;
value = dm_read_reg(
const struct dc_tiling_info *info,
const enum surface_pixel_format pixel_format)
{
+ (void)pixel_format;
uint32_t value = 0;
set_reg_field_value(value, info->gfx8.num_banks,
struct dc_plane_dcc_param *dcc,
bool horizotal_mirror)
{
+ (void)dcc;
+ (void)horizotal_mirror;
struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
enable(mem_input110);
struct dce_watermarks urgent,
uint32_t total_dest_line_time_ns)
{
+ (void)stutter_enter;
program_urgency_watermark_l(
mem_input->ctx,
urgent,
uint32_t pix_clk_khz,/* for current stream */
uint32_t total_stream_num)
{
+ (void)h_total;
+ (void)v_total;
+ (void)total_stream_num;
uint32_t addr;
uint32_t value;
uint32_t pix_dur;
struct mem_input *mi,
uint32_t total_stream_num)
{
+ (void)mi;
+ (void)total_stream_num;
}
static const struct mem_input_funcs dce110_mem_input_v_funcs = {
const struct out_csc_color_matrix *tbl_entry,
enum grph_color_adjust_option options)
{
+ (void)options;
struct dc_context *ctx = xfm_dce->base.ctx;
uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL);
bool use_set_a = (get_reg_field_value(cntl_value,
struct transform *xfm,
enum opp_regamma mode)
{
+ (void)xfm;
+ (void)mode;
// TODO: need to implement the function
}
struct timing_generator *tg,
struct dc_crtc_timing *timing)
{
+ (void)tg;
if (timing->flags.INTERLACE == 1) {
if (timing->v_front_porch < 2)
timing->v_front_porch = 2;
const struct dc_crtc_timing *timing,
enum signal_type signal)
{
+ (void)signal;
uint32_t h_blank;
uint32_t h_back_porch, hsync_offset, h_sync_start;
struct timing_generator *tg,
int source_tg_inst)
{
+ (void)source_tg_inst;
uint32_t value;
uint32_t rising_edge = 0;
uint32_t falling_edge = 0;
const enum signal_type signal,
bool use_vbios)
{
+ (void)vready_offset;
+ (void)vstartup_start;
+ (void)vupdate_offset;
+ (void)vupdate_width;
+ (void)pstate_keepout;
+ (void)signal;
if (use_vbios)
dce110_timing_generator_program_timing_generator(tg, timing);
else
const enum signal_type signal,
bool use_vbios)
{
+ (void)vready_offset;
+ (void)vstartup_start;
+ (void)vupdate_offset;
+ (void)vupdate_width;
+ (void)pstate_keepout;
+ (void)signal;
if (use_vbios)
dce110_timing_generator_program_timing_generator(tg, timing);
else
struct timing_generator *tg,
const struct dcp_gsl_params *gsl_params)
{
+ (void)gsl_params;
DC_LOG_ERROR("Timing Sync not supported on underlay pipe\n");
return;
}
struct timing_generator *tg,
int source_tg_inst)
{
+ (void)source_tg_inst;
DC_LOG_ERROR("Timing Sync not supported on underlay pipe\n");
return;
}
static void dce110_timing_generator_v_disable_vga(
struct timing_generator *tg)
{
+ (void)tg;
return;
}
struct rect *luma_viewport,
struct rect *chroma_viewport)
{
+ (void)xfm_dce;
+ (void)luma_viewport;
+ (void)chroma_viewport;
inits->h_int_scale_ratio_luma =
dc_fixpt_u2d19(data->ratios.horz) << 5;
inits->v_int_scale_ratio_luma =
struct transform *xfm,
const struct xfm_grph_csc_adjustment *adjust)
{
+ (void)xfm;
+ (void)adjust;
/* DO NOTHING*/
}
enum lb_pixel_depth depth,
const struct bit_depth_reduction_params *bit_depth_params)
{
+ (void)bit_depth_params;
struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
int pixel_depth = 0;
int expan_mode = 0;
struct dce112_compressor *cp110,
uint32_t pixels)
{
+ (void)cp110;
return 256 * ((pixels + 255) / 256);
}
struct timing_generator *tg,
int source)
{
+ (void)source;
enum trigger_source_select trig_src_select = TRIGGER_SOURCE_SELECT_LOGIC_ZERO;
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
uint32_t rising_edge = 0;
const enum signal_type signal,
bool use_vbios)
{
+ (void)vready_offset;
+ (void)vstartup_start;
+ (void)vupdate_offset;
+ (void)vupdate_width;
+ (void)pstate_keepout;
+ (void)signal;
if (use_vbios)
dce110_timing_generator_program_timing_generator(tg, timing);
else
const enum signal_type signal,
bool use_vbios)
{
+ (void)vready_offset;
+ (void)vstartup_start;
+ (void)vupdate_offset;
+ (void)vupdate_width;
+ (void)pstate_keepout;
+ (void)signal;
if (!use_vbios)
program_pix_dur(tg, timing->pix_clk_100hz);
static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
{
+ (void)dwbc;
if (caps) {
caps->adapter_id = 0; /* we only support 1 adapter currently */
caps->hw_version = DCN_VERSION_1_0;
static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
{
+ (void)params;
struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
/* disable first. */
unsigned int az_inst,
struct audio_info *audio_info)
{
+ (void)az_inst;
struct dcn31_apg *apg31 = DCN31_APG_FROM_APG(apg);
ASSERT(audio_info);
bool use_vsc_sdp_for_colorimetry,
uint32_t enable_sdp_splitting)
{
+ (void)enable_sdp_splitting;
uint32_t h_active_start;
uint32_t v_active_start;
uint32_t misc0 = 0;
const uint8_t *custom_sdp_message,
unsigned int sdp_message_size)
{
+ (void)sdp_message_size;
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
uint32_t value = 0;
uint32_t dsc_bytes_per_pixel,
uint32_t dsc_slice_width)
{
+ (void)dsc_bytes_per_pixel;
+ (void)dsc_slice_width;
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1);
uint32_t dsc_bytes_per_pixel,
uint32_t dsc_slice_width)
{
+ (void)dsc_bytes_per_pixel;
+ (void)dsc_slice_width;
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1);
uint32_t stream_enc_inst,
uint32_t link_enc_inst)
{
+ (void)stream_enc_inst;
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
ASSERT(stream_enc_inst < 5 && link_enc_inst < 5);
struct stream_encoder *enc,
bool odm_combine)
{
+ (void)enc;
+ (void)odm_combine;
}
/* setup stream encoder in dvi mode */
uint32_t stream_enc_inst,
uint32_t link_enc_inst)
{
+ (void)stream_enc_inst;
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
REG_UPDATE(STREAM_MAPPER_CONTROL,
static bool virtual_link_encoder_validate_output_with_stream(
struct link_encoder *enc,
- const struct dc_stream_state *stream) { return true; }
+ const struct dc_stream_state *stream) {
+ (void)enc;
+ (void)stream;
+ return true;
+ }
-static void virtual_link_encoder_hw_init(struct link_encoder *enc) {}
+static void virtual_link_encoder_hw_init(struct link_encoder *enc)
+{
+ (void)enc;
+}
static void virtual_link_encoder_setup(
- struct link_encoder *enc,
- enum signal_type signal) {}
+ struct link_encoder *enc, enum signal_type signal) {
+ (void)enc;
+ (void)signal;
+ }
static void virtual_link_encoder_enable_tmds_output(
struct link_encoder *enc,
enum clock_source_id clock_source,
enum dc_color_depth color_depth,
enum signal_type signal,
- uint32_t pixel_clock) {}
+ uint32_t pixel_clock) {
+ (void)enc;
+ (void)clock_source;
+ (void)color_depth;
+ (void)signal;
+ (void)pixel_clock;
+ }
static void virtual_link_encoder_enable_dp_output(
struct link_encoder *enc,
const struct dc_link_settings *link_settings,
- enum clock_source_id clock_source) {}
+ enum clock_source_id clock_source) {
+ (void)enc;
+ (void)link_settings;
+ (void)clock_source;
+ }
static void virtual_link_encoder_enable_dp_mst_output(
struct link_encoder *enc,
const struct dc_link_settings *link_settings,
- enum clock_source_id clock_source) {}
+ enum clock_source_id clock_source) {
+ (void)enc;
+ (void)link_settings;
+ (void)clock_source;
+ }
static void virtual_link_encoder_disable_output(
struct link_encoder *link_enc,
- enum signal_type signal) {}
+ enum signal_type signal) {
+ (void)link_enc;
+ (void)signal;
+ }
static void virtual_link_encoder_dp_set_lane_settings(
struct link_encoder *enc,
const struct dc_link_settings *link_settings,
- const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) {}
+ const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) {
+ (void)enc;
+ (void)link_settings;
+ (void)lane_settings;
+ }
static void virtual_link_encoder_dp_set_phy_pattern(
struct link_encoder *enc,
- const struct encoder_set_dp_phy_pattern_param *param) {}
+ const struct encoder_set_dp_phy_pattern_param *param) {
+ (void)enc;
+ (void)param;
+ }
static void virtual_link_encoder_update_mst_stream_allocation_table(
struct link_encoder *enc,
- const struct link_mst_stream_allocation_table *table) {}
+ const struct link_mst_stream_allocation_table *table) {
+ (void)enc;
+ (void)table;
+ }
static void virtual_link_encoder_connect_dig_be_to_fe(
struct link_encoder *enc,
enum engine_id engine,
- bool connect) {}
+ bool connect) {
+ (void)enc;
+ (void)engine;
+ (void)connect;
+ }
static void virtual_link_encoder_destroy(struct link_encoder **enc)
{
static void virtual_link_encoder_get_max_link_cap(struct link_encoder *enc,
struct dc_link_settings *link_settings)
{
+ (void)enc;
/* Set Default link settings */
struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
struct dc_crtc_timing *crtc_timing,
enum dc_color_space output_color_space,
bool use_vsc_sdp_for_colorimetry,
- uint32_t enable_sdp_splitting) {}
+ uint32_t enable_sdp_splitting) {
+ (void)enc;
+ (void)crtc_timing;
+ (void)output_color_space;
+ (void)use_vsc_sdp_for_colorimetry;
+ (void)enable_sdp_splitting;
+ }
static void virtual_stream_encoder_hdmi_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
int actual_pix_clk_khz,
- bool enable_audio) {}
+ bool enable_audio) {
+ (void)enc;
+ (void)crtc_timing;
+ (void)actual_pix_clk_khz;
+ (void)enable_audio;
+ }
static void virtual_stream_encoder_dvi_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
- bool is_dual_link) {}
+ bool is_dual_link) {
+ (void)enc;
+ (void)crtc_timing;
+ (void)is_dual_link;
+ }
static void virtual_stream_encoder_set_throttled_vcp_size(
struct stream_encoder *enc,
- struct fixed31_32 avg_time_slots_per_mtp)
-{}
+ struct fixed31_32 avg_time_slots_per_mtp) {
+ (void)enc;
+ (void)avg_time_slots_per_mtp;
+ }
static void virtual_stream_encoder_update_hdmi_info_packets(
struct stream_encoder *enc,
- const struct encoder_info_frame *info_frame) {}
+ const struct encoder_info_frame *info_frame) {
+ (void)enc;
+ (void)info_frame;
+ }
static void virtual_stream_encoder_stop_hdmi_info_packets(
- struct stream_encoder *enc) {}
+ struct stream_encoder *enc) {
+ (void)enc;
+ }
static void virtual_stream_encoder_set_avmute(
- struct stream_encoder *enc,
- bool enable) {}
+ struct stream_encoder *enc, bool enable) {
+ (void)enc;
+ (void)enable;
+ }
static void virtual_stream_encoder_update_dp_info_packets(
struct stream_encoder *enc,
- const struct encoder_info_frame *info_frame) {}
+ const struct encoder_info_frame *info_frame) {
+ (void)enc;
+ (void)info_frame;
+ }
static void virtual_stream_encoder_stop_dp_info_packets(
- struct stream_encoder *enc) {}
+ struct stream_encoder *enc) {
+ (void)enc;
+ }
static void virtual_stream_encoder_dp_blank(
struct dc_link *link,
- struct stream_encoder *enc) {}
+ struct stream_encoder *enc) {
+ (void)link;
+ (void)enc;
+ }
static void virtual_stream_encoder_dp_unblank(
struct dc_link *link,
struct stream_encoder *enc,
- const struct encoder_unblank_param *param) {}
+ const struct encoder_unblank_param *param) {
+ (void)enc;
+ (void)link;
+ (void)param;
+ }
static void virtual_audio_mute_control(
- struct stream_encoder *enc,
- bool mute) {}
+ struct stream_encoder *enc, bool mute) {
+ (void)enc;
+ (void)mute;
+ }
static void virtual_stream_encoder_reset_hdmi_stream_attribute(
- struct stream_encoder *enc)
-{}
+ struct stream_encoder *enc)
+{
+ (void)enc;
+}
static void virtual_enc_dp_set_odm_combine(
- struct stream_encoder *enc,
- bool odm_combine)
-{}
+ struct stream_encoder *enc, bool odm_combine) {
+ (void)enc;
+ (void)odm_combine;
+ }
static void virtual_dig_connect_to_otg(
- struct stream_encoder *enc,
- int tg_inst)
-{}
+ struct stream_encoder *enc, int tg_inst) {
+ (void)enc;
+ (void)tg_inst;
+ }
static void virtual_setup_stereo_sync(
- struct stream_encoder *enc,
- int tg_inst,
- bool enable)
-{}
+ struct stream_encoder *enc,
+ int tg_inst, bool enable) {
+ (void)enc;
+ (void)tg_inst;
+ (void)enable;
+ }
static void virtual_stream_encoder_set_dsc_pps_info_packet(
- struct stream_encoder *enc,
- bool enable,
- uint8_t *dsc_packed_pps,
- bool immediate_update)
-{}
+ struct stream_encoder *enc, bool enable, uint8_t *dsc_packed_pps,
+ bool immediate_update)
+{
+ (void)enc;
+ (void)enable;
+ (void)dsc_packed_pps;
+ (void)immediate_update;
+}
static const struct stream_encoder_funcs virtual_str_enc_funcs = {
.dp_set_odm_combine =
struct pipe_ctx *primary_pipe,
struct pipe_ctx *secondary_pipe)
{
+ (void)res_ctx;
int pipe_idx = secondary_pipe->pipe_idx;
if (!primary_pipe->plane_state)
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
+ (void)validate_mode;
int pipe_cnt, i;
bool synchronized_vblank = true;
struct resource_context *res_ctx = &context->res_ctx;
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{
+ (void)mode_lib;
+
bool MyError = false;
unsigned int DPPCycles, DISPCLKCycles;
double DSTTotalPixelsAfterScaler, TotalRepeaterDelayTime;
unsigned int *dpte_row_height,
unsigned int *meta_row_height)
{
+ (void)ViewportWidth;
unsigned int MetaRequestHeight;
unsigned int MetaRequestWidth;
unsigned int MetaSurfWidth;
double *TInitXFill,
double *TslvChk)
{
+ (void)mode_lib;
double TSlvSetup, AvgfillRate, result;
*SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime;
double *DSTYAfterScaler
)
{
+ (void)ReturnBW;
unsigned int DPPCycles, DISPCLKCycles;
double DataFabricLineDeliveryTimeLuma;
double DataFabricLineDeliveryTimeChroma;
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{
+ (void)mode_lib;
+
bool MyError = false;
double TotalRepeaterDelayTime;
double Tdm, LineTime, Tsetup;
unsigned int *dpte_row_height,
unsigned int *meta_row_height)
{
+ (void)ViewportWidth;
unsigned int MetaRequestHeight;
unsigned int MetaRequestWidth;
unsigned int MetaSurfWidth;
double *TInitXFill,
double *TslvChk)
{
+ (void)mode_lib;
double TSlvSetup, AvgfillRate, result;
*SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime;
unsigned int delivery_width,
unsigned int req_per_swath_ub)
{
+ (void)mode_lib;
double refcyc_per_delivery = 0.0;
if (vratio <= 1.0) {
const bool ignore_viewport_pos,
const bool immediate_flip_support)
{
+ (void)vm_en;
+ (void)ignore_viewport_pos;
+ (void)immediate_flip_support;
display_rq_params_st rq_param = {0};
display_dlg_sys_params_st dlg_sys_param = {0};
unsigned int cur_width,
enum cursor_bpp cur_bpp)
{
+ (void)mode_lib;
unsigned int cur_src_width = cur_width;
unsigned int cur_req_size = 0;
unsigned int cur_req_width = 0;
unsigned int delivery_width,
unsigned int req_per_swath_ub)
{
+ (void)mode_lib;
double refcyc_per_delivery = 0.0;
if (vratio <= 1.0) {
const bool ignore_viewport_pos,
const bool immediate_flip_support)
{
+ (void)vm_en;
+ (void)ignore_viewport_pos;
+ (void)immediate_flip_support;
display_rq_params_st rq_param = {0};
display_dlg_sys_params_st dlg_sys_param = {0};
unsigned int cur_width,
enum cursor_bpp cur_bpp)
{
+ (void)mode_lib;
unsigned int cur_src_width = cur_width;
unsigned int cur_req_size = 0;
unsigned int cur_req_width = 0;
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{
+ (void)mode_lib;
+ (void)XFCEnabled;
+
bool MyError = false;
unsigned int DPPCycles, DISPCLKCycles;
double DSTTotalPixelsAfterScaler, TotalRepeaterDelayTime;
unsigned int *DPDE0BytesFrame,
unsigned int *MetaPTEBytesFrame)
{
+ (void)SourcePixelFormat;
+ (void)ViewportWidth;
unsigned int MPDEBytesFrame;
unsigned int DCCMetaSurfaceBytes;
unsigned int MacroTileSizeBytes;
double *TInitXFill,
double *TslvChk)
{
+ (void)mode_lib;
double TSlvSetup, AvgfillRate, result;
*SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime;
double *final_flip_bw,
bool *ImmediateFlipSupportedForPipe)
{
+ (void)mode_lib;
double min_row_time = 0.0;
unsigned int HostVMDynamicLevels;
double TimeForFetchingMetaPTEImmediateFlip;
double *StutterEnterPlusExitWatermark,
double *MinActiveDRAMClockChangeLatencySupported)
{
+ (void)DPPCLK;
+ (void)SwathWidthSingleDPPY;
+ (void)DCFCLK;
+ (void)UrgentOutOfOrderReturn;
+ (void)ReturnBW;
+ (void)GPUVMEnable;
+ (void)dpte_group_bytes;
+ (void)MetaChunkSize;
+
double EffectiveLBLatencyHidingY;
double EffectiveLBLatencyHidingC;
double DPPOutputBufferLinesY;
double TimePerVMRequestVBlank[],
double TimePerVMRequestFlip[])
{
+ (void)VRatioPrefetchY;
+ (void)VRatioPrefetchC;
+
unsigned int meta_chunk_width;
unsigned int min_meta_chunk_width;
unsigned int meta_chunk_per_row_int;
unsigned int delivery_width,
unsigned int req_per_swath_ub)
{
+ (void)mode_lib;
double refcyc_per_delivery = 0.0;
if (vratio <= 1.0) {
const bool ignore_viewport_pos,
const bool immediate_flip_support)
{
+ (void)vm_en;
+ (void)ignore_viewport_pos;
+ (void)immediate_flip_support;
display_rq_params_st rq_param = {0};
display_dlg_sys_params_st dlg_sys_param = {0};
unsigned int cur_width,
enum cursor_bpp cur_bpp)
{
+ (void)mode_lib;
unsigned int cur_src_width = cur_width;
unsigned int cur_req_size = 0;
unsigned int cur_req_width = 0;
unsigned int *dcfclk_mhz,
unsigned int *dram_speed_mts)
{
+ (void)bw_params;
unsigned int i;
dc_assert_fp_enabled();
void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip)
{
+ (void)dcn3_0_ip;
dc_assert_fp_enabled();
if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
double *RequiredPrefetchPixDataBWChroma,
bool *NotEnoughTimeForDynamicMetadata)
{
+ (void)SwathWidthY;
+ (void)SwathWidthC;
struct vba_vars_st *v = &mode_lib->vba;
double DPPCLKDelaySubtotalPlusCNVCFormater = v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater;
bool MyError = false;
unsigned int *IndependentBlockLuma,
unsigned int *IndependentBlockChroma)
{
+ (void)SurfaceWidthChroma;
+ (void)SurfaceHeightChroma;
+ (void)BytePerPixelDETY;
+ (void)BytePerPixelDETC;
int yuv420 = 0;
int horz_div_l = 0;
int horz_div_c = 0;
unsigned int *DPDE0BytesFrame,
unsigned int *MetaPTEBytesFrame)
{
+ (void)SourcePixelFormat;
unsigned int MPDEBytesFrame = 0;
unsigned int DCCMetaSurfaceBytes = 0;
unsigned int MacroTileSizeBytes = 0;
unsigned int HTotal,
unsigned int WritebackLineBufferSize)
{
+ (void)WritebackPixelFormat;
+ (void)WritebackVRatio;
double DISPCLK_H = 0, DISPCLK_V = 0, DISPCLK_HB = 0;
DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio;
long WritebackSourceHeight,
unsigned int HTotal)
{
+ (void)WritebackPixelFormat;
+ (void)WritebackHRatio;
double CalculateWriteBackDelay = 0;
double Line_length = 0;
double Output_lines_last_notclamped = 0;
double *final_flip_bw,
bool *ImmediateFlipSupportedForPipe)
{
+ (void)mode_lib;
+ (void)HostVMMinPageSize;
double min_row_time = 0.0;
unsigned int HostVMDynamicLevelsTrips = 0;
double TimeForFetchingMetaPTEImmediateFlip = 0;
double BytePerPixelDETC[],
enum clock_change_support *DRAMClockChangeSupport)
{
+ (void)DCFCLK;
+ (void)ReturnBW;
+ (void)DPPCLK;
+ (void)DETBufferSizeC;
struct vba_vars_st *v = &mode_lib->vba;
double EffectiveLBLatencyHidingY = 0;
double EffectiveLBLatencyHidingC = 0;
double *UrgentBurstFactorChroma,
bool *NotEnoughUrgentLatencyHiding)
{
+ (void)DETBufferSizeInKByte;
+ (void)VRatioC;
double LinesInDETLuma = 0;
double LinesInDETChroma = 0;
unsigned int LinesInCursorBuffer = 0;
double TimePerVMRequestVBlank[],
double TimePerVMRequestFlip[])
{
+ (void)dpte_row_width_luma_ub;
+ (void)dpte_row_width_chroma_ub;
int num_group_per_lower_vm_stage = 0;
int num_req_per_lower_vm_stage = 0;
unsigned int k;
bool ViewportSizeSupportPerPlane[],
bool *ViewportSizeSupport)
{
+ (void)HRatioChroma;
int MaximumSwathHeightY[DC__NUM_DPP__MAX] = { 0 };
int MaximumSwathHeightC[DC__NUM_DPP__MAX] = { 0 };
int MinimumSwathHeightY = 0;
unsigned int swath_width_luma_ub[],
unsigned int swath_width_chroma_ub[])
{
+ (void)BytePerPixY;
unsigned int k, j;
long surface_width_ub_l;
long surface_height_ub_l;
unsigned int delivery_width,
unsigned int req_per_swath_ub)
{
+ (void)mode_lib;
double refcyc_per_delivery = 0.0;
if (vratio <= 1.0) {
unsigned int cur_width,
enum cursor_bpp cur_bpp)
{
+ (void)mode_lib;
unsigned int cur_src_width = cur_width;
unsigned int cur_req_size = 0;
unsigned int cur_req_width = 0;
const bool ignore_viewport_pos,
const bool immediate_flip_support)
{
+ (void)vm_en;
+ (void)ignore_viewport_pos;
+ (void)immediate_flip_support;
const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{
+ (void)mode_lib;
+ (void)HostVMMinPageSize;
+ (void)SwathWidthY;
+ (void)SwathWidthC;
+
bool MyError = false;
unsigned int DPPCycles, DISPCLKCycles;
double DSTTotalPixelsAfterScaler;
unsigned int *IndependentBlockLuma,
unsigned int *IndependentBlockChroma)
{
+ (void)SurfaceWidthChroma;
+ (void)SurfaceHeightChroma;
+ (void)BytePerPixelDETY;
+ (void)BytePerPixelDETC;
int yuv420;
int horz_div_l;
int horz_div_c;
int *DPDE0BytesFrame,
int *MetaPTEBytesFrame)
{
+ (void)SourcePixelFormat;
struct vba_vars_st *v = &mode_lib->vba;
unsigned int MPDEBytesFrame;
unsigned int DCCMetaSurfaceBytes;
unsigned int HTotal,
unsigned int WritebackLineBufferSize)
{
+ (void)WritebackPixelFormat;
+ (void)WritebackVRatio;
double DISPCLK_H, DISPCLK_V, DISPCLK_HB;
DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio;
int WritebackSourceHeight,
unsigned int HTotal)
{
+ (void)WritebackPixelFormat;
+ (void)WritebackHRatio;
double CalculateWriteBackDelay;
double Line_length;
double Output_lines_last_notclamped;
double *Z8StutterExitWatermark,
double *Z8StutterEnterPlusExitWatermark)
{
+ (void)DCFCLK;
+ (void)ReturnBW;
+ (void)DETBufferSizeC;
struct vba_vars_st *v = &mode_lib->vba;
double EffectiveLBLatencyHidingY;
double EffectiveLBLatencyHidingC;
double *UrgentBurstFactorChroma,
bool *NotEnoughUrgentLatencyHiding)
{
+ (void)VRatioC;
double LinesInDETLuma;
double LinesInDETChroma;
unsigned int LinesInCursorBuffer;
double TimePerVMRequestVBlank[],
double TimePerVMRequestFlip[])
{
+ (void)dpte_row_width_luma_ub;
+ (void)dpte_row_width_chroma_ub;
int num_group_per_lower_vm_stage;
int num_req_per_lower_vm_stage;
int k;
int *Z8NumberOfStutterBurstsPerFrame,
double *StutterPeriod)
{
+ (void)ConfigReturnBufferSizeInKByte;
+
struct vba_vars_st *v = &mode_lib->vba;
double DETBufferingTimeY;
bool ViewportSizeSupportPerPlane[],
bool *ViewportSizeSupport)
{
+ (void)HRatioChroma;
int MaximumSwathHeightY[DC__NUM_DPP__MAX];
int MaximumSwathHeightC[DC__NUM_DPP__MAX];
int MinimumSwathHeightY;
int swath_width_luma_ub[],
int swath_width_chroma_ub[])
{
+ (void)BytePerPixY;
enum odm_combine_mode MainPlaneODMCombine;
int j, k;
unsigned int delivery_width,
unsigned int req_per_swath_ub)
{
+ (void)mode_lib;
double refcyc_per_delivery = 0.0;
if (vratio <= 1.0) {
unsigned int cur_width,
enum cursor_bpp cur_bpp)
{
+ (void)mode_lib;
unsigned int cur_src_width = cur_width;
unsigned int cur_req_size = 0;
unsigned int cur_req_width = 0;
const bool ignore_viewport_pos,
const bool immediate_flip_support)
{
+ (void)cstate_en;
+ (void)pstate_en;
+ (void)vm_en;
+ (void)ignore_viewport_pos;
+ (void)immediate_flip_support;
+ (void)dlg_sys_param;
const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{
+ (void)mode_lib;
+ (void)HostVMMinPageSize;
+ (void)SwathWidthY;
+ (void)SwathWidthC;
+
bool MyError = false;
unsigned int DPPCycles, DISPCLKCycles;
double DSTTotalPixelsAfterScaler;
unsigned int *IndependentBlockLuma,
unsigned int *IndependentBlockChroma)
{
+ (void)SurfaceWidthChroma;
+ (void)SurfaceHeightChroma;
+ (void)BytePerPixelDETY;
+ (void)BytePerPixelDETC;
int yuv420;
int horz_div_l;
int horz_div_c;
int *DPDE0BytesFrame,
int *MetaPTEBytesFrame)
{
+ (void)SourcePixelFormat;
struct vba_vars_st *v = &mode_lib->vba;
unsigned int MPDEBytesFrame;
unsigned int DCCMetaSurfaceBytes;
unsigned int HTotal,
unsigned int WritebackLineBufferSize)
{
+ (void)WritebackPixelFormat;
+ (void)WritebackVRatio;
double DISPCLK_H, DISPCLK_V, DISPCLK_HB;
DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio;
int WritebackSourceHeight,
unsigned int HTotal)
{
+ (void)WritebackPixelFormat;
+ (void)WritebackHRatio;
double CalculateWriteBackDelay;
double Line_length;
double Output_lines_last_notclamped;
double *Z8StutterExitWatermark,
double *Z8StutterEnterPlusExitWatermark)
{
+ (void)DCFCLK;
+ (void)ReturnBW;
+ (void)DETBufferSizeC;
struct vba_vars_st *v = &mode_lib->vba;
double EffectiveLBLatencyHidingY;
double EffectiveLBLatencyHidingC;
double *UrgentBurstFactorChroma,
bool *NotEnoughUrgentLatencyHiding)
{
+ (void)VRatioC;
double LinesInDETLuma;
double LinesInDETChroma;
unsigned int LinesInCursorBuffer;
double TimePerVMRequestVBlank[],
double TimePerVMRequestFlip[])
{
+ (void)dpte_row_width_luma_ub;
+ (void)dpte_row_width_chroma_ub;
int num_group_per_lower_vm_stage;
int num_req_per_lower_vm_stage;
int k;
int *Z8NumberOfStutterBurstsPerFrame,
double *StutterPeriod)
{
+ (void)ConfigReturnBufferSizeInKByte;
+
struct vba_vars_st *v = &mode_lib->vba;
double DETBufferingTimeY;
bool ViewportSizeSupportPerPlane[],
bool *ViewportSizeSupport)
{
+ (void)HRatioChroma;
int MaximumSwathHeightY[DC__NUM_DPP__MAX];
int MaximumSwathHeightC[DC__NUM_DPP__MAX];
int MinimumSwathHeightY;
int swath_width_luma_ub[],
int swath_width_chroma_ub[])
{
+ (void)BytePerPixY;
enum odm_combine_mode MainPlaneODMCombine;
int j, k;
unsigned int delivery_width,
unsigned int req_per_swath_ub)
{
+ (void)mode_lib;
double refcyc_per_delivery = 0.0;
if (vratio <= 1.0) {
unsigned int cur_width,
enum cursor_bpp cur_bpp)
{
+ (void)mode_lib;
unsigned int cur_src_width = cur_width;
unsigned int cur_req_size = 0;
unsigned int cur_req_width = 0;
const bool ignore_viewport_pos,
const bool immediate_flip_support)
{
+ (void)cstate_en;
+ (void)pstate_en;
+ (void)vm_en;
+ (void)ignore_viewport_pos;
+ (void)immediate_flip_support;
+ (void)dlg_sys_param;
const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
*/
double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context)
{
+ (void)dc;
double max_vratio_pre = __DML_MAX_BW_RATIO_PRE__; // Default value is 4
int i;
void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb)
{
+ (void)soc_bb;
dc_assert_fp_enabled();
dcn3_2_soc.clock_limits[0].dcfclk_mhz = 1200.0;
}
bool ViewportSizeSupportPerSurface[],
bool *ViewportSizeSupport)
{
+ (void)HRatioChroma;
unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX];
unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX];
unsigned int RoundedUpMaxSwathSizeBytesY[DC__NUM_DPP__MAX] = { 0 };
unsigned int swath_width_luma_ub[], // per-pipe
unsigned int swath_width_chroma_ub[]) // per-pipe
{
+ (void)BytePerPixY;
unsigned int k, j;
enum odm_combine_mode MainSurfaceODMMode;
unsigned int *DPDE0BytesFrame,
unsigned int *MetaPTEBytesFrame)
{
+ (void)SourcePixelFormat;
unsigned int MPDEBytesFrame;
unsigned int DCCMetaSurfaceBytes;
unsigned int ExtraDPDEBytesFrame;
double *UrgentBurstFactorChroma,
bool *NotEnoughUrgentLatencyHiding)
{
+ (void)VRatioC;
double LinesInDETLuma;
double LinesInDETChroma;
unsigned int LinesInCursorBuffer;
unsigned int WritebackSourceHeight,
unsigned int HTotal)
{
+ (void)WritebackPixelFormat;
+ (void)WritebackHRatio;
double CalculateWriteBackDelay;
double Line_length;
double Output_lines_last_notclamped;
/* Output */
double DCFCLKState[][2])
{
+ (void)MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation;
+ (void)ReadBandwidthLuma;
+ (void)ReadBandwidthChroma;
unsigned int i, j, k;
unsigned int dummy1;
double dummy2, dummy3;
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{
+ (void)SwathWidthY;
+ (void)SwathWidthC;
double DPPCLKDelaySubtotalPlusCNVCFormater = v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater;
bool MyError = false;
unsigned int DPPCycles, DISPCLKCycles;
double *final_flip_bw,
bool *ImmediateFlipSupportedForPipe)
{
+ (void)HostVMMinPageSize;
double min_row_time = 0.0;
unsigned int HostVMDynamicLevelsTrips;
double TimeForFetchingMetaPTEImmediateFlip;
bool *USRRetrainingSupport,
double ActiveDRAMClockChangeLatencyMargin[])
{
+ (void)DCFCLK;
+ (void)ReturnBW;
unsigned int i, j, k;
unsigned int SurfaceWithMinActiveFCLKChangeMargin = 0;
unsigned int DRAMClockChangeSupportNumber = 0;
unsigned int WritebackLineBufferSize,
double DISPCLKDPPCLKVCOSpeed)
{
+ (void)WritebackPixelFormat;
+ (void)WritebackVRatio;
double DISPCLK_H, DISPCLK_V, DISPCLK_HB;
DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio;
double TimePerVMRequestVBlank[],
double TimePerVMRequestFlip[])
{
+ (void)dpte_row_width_luma_ub;
+ (void)dpte_row_width_chroma_ub;
unsigned int k;
unsigned int num_group_per_lower_vm_stage;
unsigned int num_req_per_lower_vm_stage;
unsigned int *IndependentBlockLuma,
unsigned int *IndependentBlockChroma)
{
+ (void)SurfaceWidthChroma;
+ (void)SurfaceHeightChroma;
+ (void)TilingFormat;
+ (void)BytePerPixelDETY;
+ (void)BytePerPixelDETC;
typedef enum {
REQ_256Bytes,
REQ_128BytesNonContiguous,
void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr)
{
+ (void)clk_mgr;
//TODO
}
display_e2e_pipe_params_st *pipes,
int pipe_cnt)
{
+ (void)mode_lib;
display_pipe_source_params_st *pipe_src;
display_pipe_dest_params_st *pipe_dest;
scaler_ratio_depth_st *scale_ratio_depth;
void print__data_rq_sizing_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_sizing_params_st *rq_sizing)
{
+ (void)mode_lib;
+ (void)rq_sizing;
dml_print("DML_RQ_DLG_CALC: =====================================\n");
dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST\n");
dml_print("DML_RQ_DLG_CALC: chunk_bytes = %0d\n", rq_sizing->chunk_bytes);
void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_dlg_params_st *rq_dlg_param)
{
+ (void)mode_lib;
+ (void)rq_dlg_param;
dml_print("DML_RQ_DLG_CALC: =====================================\n");
dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST\n");
dml_print(
void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_misc_params_st *rq_misc_param)
{
+ (void)mode_lib;
+ (void)rq_misc_param;
dml_print("DML_RQ_DLG_CALC: =====================================\n");
dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST\n");
dml_print(
void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param)
{
+ (void)dlg_sys_param;
+ (void)mode_lib;
dml_print("DML_RQ_DLG_CALC: =====================================\n");
dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n");
dml_print("DML_RQ_DLG_CALC: t_mclk_wm_us = %3.2f\n", dlg_sys_param->t_mclk_wm_us);
void print__data_rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_regs_st *rq_regs)
{
+ (void)mode_lib;
+ (void)rq_regs;
dml_print("DML_RQ_DLG_CALC: =====================================\n");
dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST\n");
dml_print("DML_RQ_DLG_CALC: chunk_size = 0x%0x\n", rq_regs->chunk_size);
void print__dlg_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_regs_st *dlg_regs)
{
+ (void)dlg_regs;
+ (void)mode_lib;
dml_print("DML_RQ_DLG_CALC: =====================================\n");
dml_print("DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST\n");
dml_print(
void print__ttu_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_ttu_regs_st *ttu_regs)
{
+ (void)mode_lib;
+ (void)ttu_regs;
dml_print("DML_RQ_DLG_CALC: =====================================\n");
dml_print("DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST\n");
dml_print(
unsigned int delivery_width,
unsigned int req_per_swath_ub)
{
+ (void)mode_lib;
double refcyc_per_delivery = 0.0;
if (vratio <= 1.0) {
double vinit,
double l_sw)
{
+ (void)mode_lib;
double prefill = dml_floor(vinit, 1);
double vratio_pre = 1.0;
unsigned int swath_height,
double vinit)
{
+ (void)mode_lib;
double prefill = dml_floor(vinit, 1);
unsigned int max_partial_sw_int;
enum dc_color_space input_color_space,
struct cnv_alpha_2bit_lut *alpha_2bit_lut)
{
+ (void)alpha_2bit_lut;
uint32_t pixel_format;
uint32_t alpha_en;
enum pixel_format_description fmt ;
void dpp2_dummy_program_input_lut(
struct dpp *dpp_base,
const struct dc_gamma *gamma)
-{}
+{
+ (void)dpp_base;
+ (void)gamma;
+}
static void dpp2_cnv_setup (
struct dpp *dpp_base,
struct dpp *dpp,
const struct pwl_params *params,
enum opp_regamma mode)
-{}
+{
+ (void)dpp;
+ (void)params;
+ (void)mode;
+}
static struct dpp_funcs dcn20_dpp_funcs = {
.dpp_read_state = dpp20_read_state,
bool is_color_channel_12bits,
bool is_lut_size17x17x17)
{
+ (void)is_color_channel_12bits;
uint32_t lut_mode;
struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
bool is_color_channel_12bits,
bool is_lut_size17x17x17)
{
+ (void)is_color_channel_12bits;
uint32_t lut_mode;
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
uint32_t num,
bool is_ram_a)
{
+ (void)is_ram_a;
uint32_t i;
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
uint32_t width,
uint32_t height)
{
+ (void)param;
+ (void)width;
+ (void)height;
struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
uint32_t cur_en = pos->enable ? 1 : 0;
enum dc_color_space color_space,
struct dc_csc_transform cursor_csc_color_matrix)
{
+ (void)color_space;
+ (void)cursor_csc_color_matrix;
//Since we don't have cursor matrix information, force bypass mode by passing in unknown color space
dpp401_program_cursor_csc(dpp_base, COLOR_SPACE_UNKNOWN, NULL);
}
static bool dwb3_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
{
+ (void)dwbc;
if (caps) {
caps->adapter_id = 0; /* we only support 1 adapter currently */
caps->hw_version = DCN_VERSION_3_0;
enum gpio_id *id,
uint32_t *en)
{
+ (void)mask;
switch (offset) {
/* HPD */
case REG(HPD0_DC_HPD_INT_STATUS):
enum dce_version dce_version,
enum dce_environment dce_environment)
{
+ (void)dce_environment;
switch (dce_version) {
#if defined(CONFIG_DRM_AMD_DC_SI)
case DCE_VERSION_6_0:
void dal_hw_gpio_destruct(
struct hw_gpio *pin)
{
+ (void)pin;
ASSERT(!pin->base.opened);
}
enum dce_version dce_version,
enum dce_environment dce_environment)
{
+ (void)dce_environment;
switch (dce_version) {
#if defined(CONFIG_DRM_AMD_DC_SI)
case DCE_VERSION_6_0:
unsigned int dccg_ref_freq_inKhz,
unsigned int *dchub_ref_freq_inKhz)
{
+ (void)dccg_ref_freq_inKhz;
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
uint32_t ref_div = 0;
uint32_t ref_en = 0;
unsigned int dccg_ref_freq_inKhz,
unsigned int *dchub_ref_freq_inKhz)
{
+ (void)dccg_ref_freq_inKhz;
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
uint32_t ref_div = 0;
uint32_t ref_en = 0;
unsigned int refclk_mhz,
bool safe_to_lower)
{
+ (void)refclk_mhz;
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
bool wm_pending = false;
unsigned int refclk_mhz,
bool safe_to_lower)
{
+ (void)refclk_mhz;
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
bool wm_pending = false;
unsigned int refclk_mhz,
bool safe_to_lower)
{
+ (void)refclk_mhz;
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
bool wm_pending = false;
unsigned int refclk_mhz,
bool safe_to_lower)
{
+ (void)refclk_mhz;
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
bool wm_pending = false;
static void hubbub42_set_request_limit(struct hubbub *hubbub, int memory_channel_count, int words_per_channel)
{
+ (void)memory_channel_count;
+ (void)words_per_channel;
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
uint32_t request_limit = 96; //MAX(12 * memory_channel_count, 96);
const struct dc_tiling_info *info,
const enum surface_pixel_format pixel_format)
{
+ (void)pixel_format;
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
REG_UPDATE_6(DCSURF_ADDR_CONFIG,
bool horizontal_mirror,
unsigned int compat_level)
{
+ (void)compat_level;
hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
hubp1_program_tiling(hubp, tiling_info, format);
hubp1_program_size(hubp, format, plane_size, dcc);
const struct dc_tiling_info *info,
const enum surface_pixel_format pixel_format)
{
+ (void)pixel_format;
REG_UPDATE_3(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
bool horizontal_mirror,
unsigned int compat_level)
{
+ (void)compat_level;
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
const struct dc_tiling_info *info,
const enum surface_pixel_format pixel_format)
{
+ (void)pixel_format;
REG_UPDATE_4(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
bool horizontal_mirror,
unsigned int compat_level)
{
+ (void)compat_level;
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
hubp3_dcc_control_sienna_cichlid(hubp, dcc);
bool horizontal_mirror,
unsigned int compat_level)
{
+ (void)compat_level;
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
hubp3_dcc_control_sienna_cichlid(hubp, dcc);
const struct dc_tiling_info *info,
const enum surface_pixel_format pixel_format)
{
+ (void)pixel_format;
/* DCSURF_ADDR_CONFIG still shows up in reg spec, but does not need to be programmed for DCN4x
* All 4 fields NUM_PIPES, PIPE_INTERLEAVE, MAX_COMPRESSED_FRAGS and NUM_PKRS are irrelevant.
*
const struct plane_size *plane_size,
struct dc_plane_dcc_param *dcc)
{
+ (void)dcc;
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
uint32_t pitch, pitch_c;
bool use_pitch_c = false;
bool horizontal_mirror,
unsigned int compat_level)
{
+ (void)compat_level;
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
hubp401_dcc_control(hubp, dcc);
bool horizontal_mirror,
unsigned int compat_level)
{
+ (void)compat_level;
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
hubp3_dcc_control_sienna_cichlid(hubp, dcc);
struct dc_context *ctx,
bool clock_gating)
{
+ (void)ctx;
+ (void)clock_gating;
/*TODO*/
}
dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *plane_state)
{
+ (void)dc;
struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
const struct dc_transfer_func *tf = NULL;
struct ipp_prescale_params prescale_params = { 0 };
dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
const struct dc_stream_state *stream)
{
+ (void)dc;
struct transform *xfm = pipe_ctx->plane_res.xfm;
xfm->funcs->opp_power_on_regamma_lut(xfm, true);
struct dc_state *context,
struct dc *dc)
{
+ (void)context;
struct dc_stream_state *stream = pipe_ctx->stream;
struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
pipe_ctx[pipe_ctx->pipe_idx];
static void update_plane_addr(const struct dc *dc,
struct pipe_ctx *pipe_ctx)
{
+ (void)dc;
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
if (plane_state == NULL)
int group_size,
struct pipe_ctx *grouped_pipes[])
{
+ (void)state;
+ (void)group_index;
struct dcp_gsl_params gsl_params = { 0 };
int i;
DC_LOGGER_INIT(dc->ctx);
static void dce110_init_pipes(struct dc *dc, struct dc_state *context)
{
+ (void)context;
+ (void)dc;
// Do nothing
}
struct dc *dc,
struct dc_state *context)
{
+ (void)dc;
+ (void)context;
}
static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)
{
+ (void)state;
struct dce_hwseq *hws = dc->hwseq;
int fe_idx = pipe_ctx->plane_res.mi ?
pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
struct resource_pool *res_pool,
struct pipe_ctx *pipe_ctx)
{
+ (void)dc;
+ (void)res_pool;
+ (void)pipe_ctx;
/* do nothing*/
}
uint16_t *matrix,
int opp_id)
{
+ (void)dc;
+ (void)colorspace;
+ (void)matrix;
+ (void)opp_id;
int i;
struct out_csc_color_matrix tbl_entry;
enum clock_source_id clock_source,
uint32_t pixel_clock)
{
+ (void)link_res;
link->link_enc->funcs->enable_lvds_output(
link->link_enc,
clock_source,
enum dc_color_depth color_depth,
uint32_t pixel_clock)
{
+ (void)link_res;
link->link_enc->funcs->enable_tmds_output(
link->link_enc,
clock_source,
struct dc_bios *dcb,
enum pipe_gating_control power_gating)
{
+ (void)dc;
+ (void)controller_id;
+ (void)dcb;
+ (void)power_gating;
/* disable for bringup */
#if 0
enum bp_result bp_result = BP_RESULT_OK;
struct dc_log_buffer_ctx *log_ctx,
uint32_t ref_cycle)
{
+ (void)log_ctx;
const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
static const unsigned int frac = 1000;
uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
static void log_mpc_crc(struct dc *dc,
struct dc_log_buffer_ctx *log_ctx)
{
+ (void)log_ctx;
struct dc_context *dc_ctx = dc->ctx;
struct dce_hwseq *hws = dc->hwseq;
static void dcn10_log_color_state(struct dc *dc,
struct dc_log_buffer_ctx *log_ctx)
{
+ (void)log_ctx;
struct dc_context *dc_ctx = dc->ctx;
struct resource_pool *pool = dc->res_pool;
bool is_gamut_remap_available = false;
bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
{
+ (void)dc;
struct hubp *hubp = pipe_ctx->plane_res.hubp;
struct timing_generator *tg = pipe_ctx->stream_res.tg;
struct dc_state *context,
struct dc *dc)
{
+ (void)context;
struct dc_stream_state *stream = pipe_ctx->stream;
enum dc_color_space color_space;
struct tg_color black_color = {0};
struct pipe_ctx *pipe_ctx,
struct dc_state *context)
{
+ (void)context;
int i;
struct dc_link *link;
DC_LOGGER_INIT(dc->ctx);
void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)
{
+ (void)state;
struct dce_hwseq *hws = dc->hwseq;
DC_LOGGER_INIT(dc->ctx);
void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
{
+ (void)dc;
bool addr_patched = false;
PHYSICAL_ADDRESS_LOC addr;
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *plane_state)
{
+ (void)dc;
struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
const struct dc_transfer_func *tf = NULL;
bool result = true;
int group_size,
struct pipe_ctx *grouped_pipes[])
{
+ (void)group_index;
struct output_pixel_processor *opp;
struct timing_generator *tg;
int i, width = 0, height = 0, master;
int group_size,
struct pipe_ctx *grouped_pipes[])
{
+ (void)group_index;
struct output_pixel_processor *opp;
struct timing_generator *tg;
int i, width = 0, height = 0;
struct vm_system_aperture_param *apt,
struct dce_hwseq *hws)
{
+ (void)hubp1;
PHYSICAL_ADDRESS_LOC physical_page_number;
uint32_t logical_addr_low;
uint32_t logical_addr_high;
struct vm_context0_param *vm0,
struct dce_hwseq *hws)
{
+ (void)hubp1;
PHYSICAL_ADDRESS_LOC fb_base;
PHYSICAL_ADDRESS_LOC fb_offset;
uint32_t fb_base_value;
struct pipe_ctx *pipe_ctx,
struct dc_state *context)
{
+ (void)context;
struct dce_hwseq *hws = dc->hwseq;
if (dc->debug.sanity_checks) {
uint16_t *matrix,
int opp_id)
{
+ (void)dc;
+ (void)opp_id;
if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {
struct dc_bios *dcb,
enum pipe_gating_control power_gating)
{
+ (void)dc;
+ (void)controller_id;
+ (void)dcb;
+ (void)power_gating;
return true;
}
uint32_t clk_khz,
uint32_t stepping)
{
+ (void)stepping;
struct dc_state *context = dc->current_state;
struct dc_clock_config clock_cfg = {0};
struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk;
void dcn20_log_color_state(struct dc *dc,
struct dc_log_buffer_ctx *log_ctx)
{
+ (void)log_ctx;
struct dc_context *dc_ctx = dc->ctx;
struct resource_pool *pool = dc->res_pool;
bool is_gamut_remap_available = false;
struct pipe_ctx *pipe_ctx,
bool enable_triple_buffer)
{
+ (void)dc;
if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
pipe_ctx->plane_res.hubp,
void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
{
+ (void)context;
+ (void)dc;
struct pipe_ctx *odm_pipe;
int opp_cnt = 1;
int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
struct dc_state *context)
{
+ (void)context;
//if (dc->debug.sanity_checks) {
// dcn10_verify_allow_pstate_change_high(dc);
//}
struct dc_virtual_addr_space_config *va_config,
int vmid)
{
+ (void)hws;
struct dcn_hubbub_virt_addr_config config;
if (vmid == 0) {
int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
{
+ (void)hws;
struct dcn_hubbub_phys_addr_config config;
config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
struct pipe_ctx *pipe_ctx,
struct dc_state *context)
{
+ (void)context;
struct dc_link *link = pipe_ctx->stream->link;
const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
struct dccg *dccg = dc->res_pool->dccg;
const struct tg_color *solid_color,
int width, int height, int offset)
{
+ (void)dc;
pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
color_space, color_depth, solid_color, width, height, offset);
}
void dcn30_log_color_state(struct dc *dc,
struct dc_log_buffer_ctx *log_ctx)
{
+ (void)log_ctx;
struct dc_context *dc_ctx = dc->ctx;
struct resource_pool *pool = dc->res_pool;
bool is_gamut_remap_available = false;
const struct tg_color *solid_color,
int width, int height, int offset)
{
+ (void)dc;
pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
color_space, color_depth, solid_color, width, height, offset);
}
struct timing_generator *tg,
struct dc_underflow_debug_data *out_data)
{
+ (void)tg;
struct hubbub *hubbub = dc->res_pool->hubbub;
if (hubbub) {
void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on)
{
+ (void)dpp_inst;
+ (void)hws;
+ (void)power_on;
/*DCN303 removes PG registers*/
}
void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
{
+ (void)hubp_inst;
+ (void)hws;
+ (void)power_on;
/*DCN303 removes PG registers*/
}
void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on)
{
+ (void)dsc_inst;
+ (void)hws;
+ (void)power_on;
/*DCN303 removes PG registers*/
}
void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)
{
+ (void)enable;
+ (void)hws;
/*DCN303 removes PG registers*/
}
int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
{
+ (void)hws;
struct dcn_hubbub_phys_addr_config config = {0};
config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
struct pipe_ctx *pipe_ctx,
struct dc_state *context)
{
+ (void)context;
struct dc_link *link;
if (pipe_ctx->stream_res.stream_enc == NULL) {
void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
{
+ (void)context;
struct pipe_ctx *odm_pipe;
int opp_cnt = 0;
int opp_inst[MAX_PIPES] = {0};
struct pipe_ctx *pipe_ctx,
const struct dc_stream_state *stream)
{
+ (void)dc;
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
const struct pwl_params *params = NULL;
void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
{
+ (void)context;
struct pipe_ctx *odm_pipe;
int opp_cnt = 0;
int opp_inst[MAX_PIPES] = {0};
void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
{
+ (void)context;
struct pipe_ctx *odm_pipe;
int opp_cnt = 0;
int opp_inst[MAX_PIPES] = {0};
void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
struct dc_state *context)
{
+ (void)context;
struct dpp *dpp = pipe_ctx->plane_res.dpp;
/* enable DCFCLK current DCHUB */
struct pipe_ctx *pipe_ctx,
const struct dc_stream_state *stream)
{
+ (void)dc;
int mpcc_id = pipe_ctx->plane_res.hubp->inst;
struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
const struct pwl_params *params = NULL;
struct drr_params *params,
unsigned int *event_triggers)
{
+ (void)dc;
struct dc_stream_state *stream = pipe_ctx->stream;
int i;
struct dc_state *context,
bool lock)
{
+ (void)context;
/* use always for now */
union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
struct pipe_ctx *pipe_ctx,
struct dc_state *context)
{
+ (void)context;
struct dc_link *link = pipe_ctx->stream->link;
const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
struct dc_state *context,
struct block_sequence_state *seq_state)
{
+ (void)context;
struct dwbc *dwb;
struct mcif_wb *mcif_wb;
struct dc_state *context,
struct block_sequence_state *seq_state)
{
+ (void)context;
struct dce_hwseq *hws = dc->hwseq;
uint32_t org_ip_request_cntl = 0;
struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *plane_state)
{
+ (void)dc;
struct dpp *dpp = pipe_ctx->plane_res.dpp;
if (dpp && dpp->funcs->dpp_cm_hist_control)
}
void dcn42_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
{
+ (void)dc;
struct crtc_stereo_flags flags = { 0 };
struct dc_stream_state *stream = pipe_ctx->stream;
const struct irq_source_info *info,
bool enable)
{
+ (void)enable;
DC_LOG_ERROR("%s: called for non-implemented irq source, src_id=%u, ext_id=%u\n",
__func__, info->src_id, info->ext_id);
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
switch (src_id) {
case VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0:
return DC_IRQ_SOURCE_VBLANK1;
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
+ (void)src_id;
+ (void)ext_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
+ (void)src_id;
+ (void)ext_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
+ (void)src_id;
+ (void)ext_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
+ (void)src_id;
+ (void)ext_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
static enum dc_irq_source to_dal_irq_source_dcn302(struct irq_service *irq_service, uint32_t src_id, uint32_t ext_id)
{
+ (void)ext_id;
+ (void)irq_service;
+ (void)src_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
+ (void)src_id;
+ (void)ext_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
+ (void)src_id;
+ (void)ext_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
+ (void)src_id;
+ (void)ext_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
+ (void)src_id;
+ (void)ext_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
+ (void)src_id;
+ (void)ext_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
+ (void)src_id;
+ (void)ext_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
+ (void)src_id;
+ (void)ext_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
+ (void)src_id;
+ (void)ext_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
+ (void)src_id;
+ (void)ext_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
uint32_t src_id,
uint32_t ext_id)
{
+ (void)irq_service;
+ (void)src_id;
+ (void)ext_id;
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
struct dc_link_settings *link_setting,
bool skip_video_pattern)
{
+ (void)skip_video_pattern;
struct pipe_ctx *pipes[MAX_PIPES];
struct dc_state *state = link->dc->current_state;
struct dc_stream_update stream_update = { 0 };
enum dp_test_pattern test_pattern,
enum dp_test_pattern_color_space test_pattern_color_space)
{
+ (void)test_pattern_color_space;
enum controller_dp_test_pattern controller_test_pattern;
enum dc_color_depth color_depth = pipe_ctx->
stream->timing.display_color_depth;
const struct dc_link_settings *link_settings,
const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
{
+ (void)link;
+ (void)link_res;
+ (void)link_settings;
+ (void)lane_settings;
}
static void enable_dpia_link_output(struct dc_link *link,
enum clock_source_id clock_source,
const struct dc_link_settings *link_settings)
{
+ (void)signal;
+ (void)clock_source;
if (!link_res->hpo_dp_link_enc) {
DC_LOG_ERROR("%s: invalid hpo_dp_link_enc\n", __func__);
return;
const struct dc_link_settings *link_settings,
const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
{
+ (void)link;
link_res->hpo_dp_link_enc->funcs->set_ffe(
link_res->hpo_dp_link_enc,
link_settings,
const struct link_resource *link_res,
const struct link_mst_stream_allocation_table *table)
{
+ (void)link;
link_res->hpo_dp_link_enc->funcs->update_stream_allocation_table(
link_res->hpo_dp_link_enc,
table);
void setup_hpo_dp_audio_output(struct pipe_ctx *pipe_ctx,
struct audio_output *audio_output, uint32_t audio_inst)
{
+ (void)audio_output;
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup(
pipe_ctx->stream_res.hpo_dp_stream_enc,
audio_inst,
bool can_use_hpo_dp_link_hwss(const struct dc_link *link,
const struct link_resource *link_res)
{
+ (void)link;
return link_res->hpo_dp_link_enc != NULL;
}
static void dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern(struct dc_link *link,
struct encoder_set_dp_phy_pattern_param *tp_params)
{
+ (void)tp_params;
uint8_t clk_src = 0xC4;
uint8_t pattern = 0x4F; /* SQ128 */
void virtual_setup_stream_encoder(struct pipe_ctx *pipe_ctx)
{
+ (void)pipe_ctx;
}
void virtual_setup_stream_attribute(struct pipe_ctx *pipe_ctx)
{
+ (void)pipe_ctx;
}
void virtual_reset_stream_encoder(struct pipe_ctx *pipe_ctx)
{
+ (void)pipe_ctx;
}
static void virtual_disable_link_output(struct dc_link *link,
const struct link_resource *link_res,
enum signal_type signal)
{
+ (void)link;
+ (void)link_res;
+ (void)signal;
}
static const struct link_hwss virtual_link_hwss = {
static bool should_verify_link_capability_destructively(struct dc_link *link,
enum dc_detect_reason reason)
{
+ (void)reason;
bool destrictive = false;
struct dc_link_settings max_link_cap;
bool is_link_enc_unavailable = false;
*/
enum dc_status link_validate_dp_tunnel_bandwidth(const struct dc *dc, const struct dc_state *new_ctx)
{
+ (void)dc;
struct dc_validation_dpia_set dpia_link_sets[MAX_DPIA_NUM] = { 0 };
uint8_t link_count = 0;
enum dc_status result = DC_OK;
struct dc_link *link,
const struct link_training_settings *link_training_setting)
{
+ (void)link_training_setting;
enum link_training_result status = LINK_TRAINING_SUCCESS;
union lane_status lane_status;
union lane_align_status_updated dpcd_lane_status_updated;
enum dc_dp_training_pattern pattern,
uint32_t offset)
{
+ (void)offset;
enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
switch (pattern) {
const struct link_resource *link_res,
struct link_training_settings *lt_settings)
{
+ (void)link_res;
/* Assumption: assume hardware has transmitted eq pattern */
enum dc_status status = DC_OK;
enum link_training_result result = LINK_TRAINING_SUCCESS;
struct dc_link *link,
struct link_training_settings *lt_settings)
{
+ (void)link;
union dpia_set_config_data data;
data.raw = 0;
struct link_training_settings *lt_settings,
uint32_t hop)
{
+ (void)link_res;
enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0;
uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */
enum dc_status status = DC_ERROR_UNEXPECTED;
const struct link_resource *link_res,
struct link_training_settings *lt_settings)
{
+ (void)link_res;
enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0;
enum dc_status status;
uint32_t retries_cr = 0; /* Number of consecutive attempts with same VS or PE. */
struct link_training_settings *lt_settings,
uint32_t hop)
{
+ (void)link_res;
enum link_training_result result = LINK_TRAINING_EQ_FAIL_EQ;
uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */
uint32_t retries_eq = 0;
const struct link_resource *link_res,
struct link_training_settings *lt_settings)
{
+ (void)link_res;
enum link_training_result result = LINK_TRAINING_EQ_FAIL_EQ;
uint32_t retries_eq = 0;
enum dc_status status;
const struct dc_link_settings *link_setting,
bool skip_video_pattern)
{
+ (void)skip_video_pattern;
enum link_training_result result;
struct link_training_settings lt_settings = {0};
uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */
uint8_t * const reduced_data,
const uint32_t reduced_size)
{
+ (void)extended_size;
const uint32_t offset = reduced_address - extended_address;
/*
bool rate_2x_mode,
struct mpc_dwb_flow_control *flow_control)
{
+ (void)enable;
+ (void)rate_2x_mode;
+ (void)flow_control;
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
/* Always disable mpc out rate and flow control.
bool is_lut_size17x17x17,
uint32_t rmu_idx)
{
+ (void)is_color_channel_12bits;
uint32_t lut_mode;
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
bool is_lut_size17x17x17,
uint32_t mpcc_id)
{
+ (void)is_color_channel_12bits;
uint32_t lut_mode;
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
enum dc_color_depth color_dpth,
enum signal_type signal)
{
+ (void)color_sp;
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
const enum signal_type signal,
bool use_vbios)
{
+ (void)use_vbios;
struct dc_crtc_timing patched_crtc_timing;
uint32_t asic_blank_end;
uint32_t asic_blank_start;
struct timing_generator *optc,
uint32_t early_cntl)
{
+ (void)optc;
+ (void)early_cntl;
/* asic design change, do not need this control
* empty for share caller logic
*/
static void optc1_enable_stereo(struct timing_generator *optc,
const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
{
+ (void)timing;
struct optc *optc1 = DCN10TG_FROM_TG(optc);
if (flags) {
void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
int segment_width, int last_segment_width)
{
+ (void)last_segment_width;
struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t memory_mask;
uint8_t master_clock_divider,
uint8_t slave_clock_divider)
{
+ (void)slave_clock_divider;
/* accessing slave OTG registers */
struct optc *optc1 = DCN10TG_FROM_TG(optc_slave);
void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
int segment_width, int last_segment_width)
{
+ (void)last_segment_width;
struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t memory_mask = 0;
static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
int segment_width, int last_segment_width)
{
+ (void)last_segment_width;
struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t memory_mask = 0;
int mem_count_per_opp = (segment_width + 2559) / 2560;
static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
int segment_width, int last_segment_width)
{
+ (void)last_segment_width;
struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t memory_mask = 0;
int h_active = segment_width * opp_cnt;
static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
int segment_width, int last_segment_width)
{
+ (void)last_segment_width;
struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t memory_mask = 0;
int h_active = segment_width * opp_cnt;
static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
int segment_width, int last_segment_width)
{
+ (void)last_segment_width;
struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t memory_mask = 0;
int h_active = segment_width * opp_cnt;
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dce110_link_encoder *enc110 =
kzalloc_obj(struct dce110_link_encoder);
int link_regs_id;
struct dc_state *context,
struct dc_stream_state *stream)
{
+ (void)dc;
struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
if (!pipe_ctx)
struct dc_state *context,
enum dc_validate_mode validate_mode)
{
+ (void)validate_mode;
int i;
bool at_least_one_pipe = false;
struct dc_stream_state *stream = NULL;
struct dc *dc,
struct dc_state *context)
{
+ (void)dc;
if (!dce100_validate_surface_sets(context))
return DC_FAIL_SURFACE_VALIDATE;
enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
{
+ (void)caps;
if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
return DC_OK;
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dce110_link_encoder *enc110 =
kzalloc_obj(struct dce110_link_encoder);
int link_regs_id;
struct dc_state *context,
enum dc_validate_mode validate_mode)
{
+ (void)validate_mode;
bool result = false;
DC_LOG_BANDWIDTH_CALCS(
static enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
struct dc_caps *caps)
{
+ (void)caps;
if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) ||
((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))
return DC_FAIL_SURFACE_VALIDATE;
struct dc *dc,
struct dc_state *context)
{
+ (void)dc;
if (!dce110_validate_surface_sets(context))
return DC_FAIL_SURFACE_VALIDATE;
const struct resource_pool *pool,
const struct pipe_ctx *opp_head_pipe)
{
+ (void)cur_ctx;
struct dc_stream_state *stream = opp_head_pipe->stream;
struct dc *dc = stream->ctx->dc;
struct dce_hwseq *hws = dc->hwseq;
struct dce110_resource_pool *pool,
struct hw_asic_id asic_id)
{
+ (void)asic_id;
unsigned int i;
struct dc_context *ctx = dc->ctx;
struct dc_bios *bp;
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dce110_link_encoder *enc110 =
kzalloc_obj(struct dce110_link_encoder);
int link_regs_id;
const struct resource_pool *pool,
const struct dc_stream_state *const stream)
{
+ (void)res_ctx;
switch (stream->link->link_enc->transmitter) {
case TRANSMITTER_UNIPHY_A:
return pool->clock_sources[DCE112_CLK_SRC_PLL0];
struct dc_state *context,
struct dc_stream_state *stream)
{
+ (void)dc;
struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
if (!pipe_ctx)
struct dc_state *context,
enum dc_validate_mode validate_mode)
{
+ (void)validate_mode;
bool result = false;
DC_LOG_BANDWIDTH_CALCS(
struct dc *dc,
struct dc_state *context)
{
+ (void)dc;
if (!dce112_validate_surface_sets(context))
return DC_FAIL_SURFACE_VALIDATE;
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dce110_link_encoder *enc110 =
kzalloc_obj(struct dce110_link_encoder);
int link_regs_id;
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dce110_link_encoder *enc110 =
kzalloc_obj(struct dce110_link_encoder);
int link_regs_id;
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dcn10_link_encoder *enc10 =
kzalloc_obj(struct dcn10_link_encoder);
int link_regs_id;
struct dc_state *context,
struct dc_stream_state *stream)
{
+ (void)dc;
struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
if (!pipe_ctx)
const struct resource_pool *pool,
const struct pipe_ctx *opp_head_pipe)
{
+ (void)cur_ctx;
struct resource_context *res_ctx = &new_ctx->res_ctx;
struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);
struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dcn20_link_encoder *enc20 =
kzalloc_obj(struct dcn20_link_encoder);
int link_regs_id;
enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
{
+ (void)dc;
enum dc_status status = DC_OK;
struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
struct pipe_ctx *primary_pipe,
struct pipe_ctx *secondary_pipe)
{
+ (void)res_ctx;
int pipe_idx = secondary_pipe->pipe_idx;
struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
const struct resource_pool *pool,
const struct pipe_ctx *primary_pipe)
{
+ (void)pool;
struct pipe_ctx *secondary_pipe = NULL;
if (dc && primary_pipe) {
const struct resource_pool *pool,
const struct pipe_ctx *opp_head)
{
+ (void)cur_ctx;
struct resource_context *res_ctx = &new_ctx->res_ctx;
struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(res_ctx, opp_head->stream);
struct pipe_ctx *sec_dpp_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, otg_master);
static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
{
+ (void)hw_internal_rev;
return DML_PROJECT_NAVI10v2;
}
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dcn21_link_encoder *enc21 =
kzalloc_obj(struct dcn21_link_encoder);
int link_regs_id;
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dcn20_link_encoder *enc20 =
kzalloc_obj(struct dcn20_link_encoder);
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dcn20_link_encoder *enc20 =
kzalloc_obj(struct dcn20_link_encoder);
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dcn20_link_encoder *enc20 = kzalloc_obj(struct dcn20_link_encoder);
if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dcn20_link_encoder *enc20 = kzalloc_obj(struct dcn20_link_encoder);
if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dcn20_link_encoder *enc20 =
kzalloc_obj(struct dcn20_link_encoder);
struct pipe_ctx *pipes,
struct audio_output *audio_output)
{
+ (void)link_setting;
struct dc_state *state = link->dc->current_state;
int i;
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dcn20_link_encoder *enc20 =
kzalloc_obj(struct dcn20_link_encoder);
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dcn20_link_encoder *enc20 =
kzalloc_obj(struct dcn20_link_encoder);
struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
+ (void)ctx;
struct dcn20_link_encoder *enc20 =
kzalloc_obj(struct dcn20_link_encoder);
struct pipe_ctx *pipe_ctx,
bool ignore_cursor_buf)
{
+ (void)dc;
struct hubp *hubp = pipe_ctx->plane_res.hubp;
uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;
uint32_t cursor_mall_size_bytes = 0;
static void dcn42_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
{
+ (void)bw_params;
dc_assert_fp_enabled();
if (dc->current_state && dc->current_state->bw_ctx.dml2)
struct dc_state *state,
const struct dc_stream_state *stream)
{
+ (void)state;
+ (void)stream;
return dc->caps.max_cursor_size;
}
static struct resource_funcs dcn42_res_pool_funcs = {
static void apply_soc_bb_updates(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)
{
+ (void)config;
/* Individual modification can be overwritten even if it was obtained by a previous function.
* Modifications are acquired in order of priority (lowest to highest).
*/
projects / thirdparty / linux.git / commitdiff
