////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
+// //
+// test_memory_old //
+// //
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
-static __attribute((noinline)) void test_memory ( void )
+static __attribute((noinline)) void test_memory_old ( void )
{
printf("Integer loads\n");
////////////////////////////////////////////////////////////////
printf("STL{R,RH,RB} (entirely MISSING)\n");
-
-} /* end of test_memory() */
+} /* end of test_memory_old() */
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
+// //
+// test_memory_new //
+// //
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
free(area); \
}
-static __attribute__((noinline)) void test_memory2 ( void )
+
+static __attribute__((noinline)) void test_memory_new ( void )
{
////////////////////////////////////////////////////////////////
printf("LDR,STR (immediate, uimm12)");
MEM_TEST("stp w13, w23, [x5, #-40]", 0, 0);
////////////////////////////////////////////////////////////////
-printf("LDR (literal, int reg) (DONE ABOVE)\n");
+printf("LDR (literal, int reg) (done above by test_memory_old)\n");
////////////////////////////////////////////////////////////////
-printf("{LD,ST}R (integer register) (entirely MISSING)\n");
+printf("{LD,ST}R (integer register)\n");
MEM_TEST("str x13, [x5, x6]", 12, -4);
MEM_TEST("str x13, [x5, x6, lsl #3]", 12, -4);
MEM_TEST("str x13, [x5, w6, uxtw]", 12, 4);
MEM_TEST("ldrsb w13, [x5, #56]", -16, 4);
////////////////////////////////////////////////////////////////
-printf("LDRS{B,H,W} (simm9, upd) (upd check is MISSING)\n");
+printf("LDRS{B,H,W} (simm9, upd)\n");
MEM_TEST("ldrsw x13, [x5, #-24]!", -16, 4);
MEM_TEST("ldrsh x13, [x5, #-20]!", -16, 4);
MEM_TEST("ldrsh w13, [x5, #-44]!", -16, 4);
////////////////////////////////////////////////////////////////
printf("LDP,STP (immediate, simm7) (FP&VEC)\n");
-MEM_TEST("stp q17, q18, [x5, 32]", -16, 4);
-MEM_TEST("stp q17, q18, [x5, 32]!", -16, 4);
-MEM_TEST("stp q17, q18, [x5], 32", -16, 4);
+MEM_TEST("stp q17, q18, [x5, 16]", -15, 4);
+MEM_TEST("stp q19, q18, [x5, 32]!", -11, 4);
+MEM_TEST("stp q20, q17, [x5], -48", -7, 4);
-MEM_TEST("stp d17, d18, [x5, 32]", -16, 4);
-MEM_TEST("stp d17, d18, [x5, 32]!", -16, 4);
-MEM_TEST("stp d17, d18, [x5], 32", -16, 4);
+MEM_TEST("stp d18, d17, [x5, 16]", -15, 4);
+MEM_TEST("stp d17, d19, [x5, 32]!", -11, 4);
+MEM_TEST("stp d20, d18, [x5], -48", -7, 4);
-//MEM_TEST("stp s17, s18, [x5, 32]", -16, 4);
-//MEM_TEST("stp s17, s18, [x5, 32]!", -16, 4);
-//MEM_TEST("stp s17, s18, [x5], 32", -16, 4);
+MEM_TEST("stp s17, s18, [x5, 16]", -15, 4);
+MEM_TEST("stp s19, s18, [x5, 32]!", -11, 4);
+MEM_TEST("stp s20, s17, [x5], -48", -7, 4);
-MEM_TEST("ldp q17, q18, [x5, 32]", -16, 4);
-MEM_TEST("ldp q17, q18, [x5, 32]!", -16, 4);
-MEM_TEST("ldp q17, q18, [x5], 32", -16, 4);
+MEM_TEST("ldp q17, q18, [x5, 16]", -15, 4);
+MEM_TEST("ldp q18, q19, [x5, 32]!", -11, 4);
+MEM_TEST("ldp q19, q20, [x5], -48", -7, 4);
+
+MEM_TEST("ldp d20, d17, [x5, 16]", -15, 4);
+MEM_TEST("ldp d17, d18, [x5, 32]!", -11, 4);
+MEM_TEST("ldp d18, d19, [x5], -48", -7, 4);
+
+MEM_TEST("ldp s19, s20, [x5, 16]", -15, 4);
+MEM_TEST("ldp s20, s17, [x5, 32]!", -11, 4);
+MEM_TEST("ldp s17, s18, [x5], -48", -7, 4);
+
+////////////////////////////////////////////////////////////////
+printf("LDNP,STNP (immediate, simm7) (FP&VEC, w/ nontemporal hint)\n");
-MEM_TEST("ldp d17, d18, [x5, 32]", -16, 4);
-MEM_TEST("ldp d17, d18, [x5, 32]!", -16, 4);
-MEM_TEST("ldp d17, d18, [x5], 32", -16, 4);
+MEM_TEST("stnp q18, q17, [x5, 16]", -15, 4);
+MEM_TEST("stnp d20, d19, [x5, 40]", -15, 4);
+MEM_TEST("stnp s19, s18, [x5, 68]", -15, 4);
-//MEM_TEST("ldp s17, s18, [x5, 32]", -16, 4);
-//MEM_TEST("ldp s17, s18, [x5, 32]!", -16, 4);
-//MEM_TEST("ldp s17, s18, [x5], 32", -16, 4);
+MEM_TEST("ldnp q18, q17, [x5, 16]", -15, 4);
+MEM_TEST("ldnp d17, d20, [x5, 40]", -15, 4);
+MEM_TEST("ldnp s20, s19, [x5, 68]", -15, 4);
////////////////////////////////////////////////////////////////
printf("{LD,ST}R (vector register)\n");
-#if 0
MEM_TEST("str q17, [x5, x6]", 12, -4);
MEM_TEST("str q17, [x5, x6, lsl #4]", 12, -4);
MEM_TEST("str q17, [x5, w6, uxtw]", 12, 4);
MEM_TEST("ldr q17, [x5, w6, uxtw #4]", 12, 4);
MEM_TEST("ldr q17, [x5, w6, sxtw]", 12, 4);
MEM_TEST("ldr q17, [x5, w6, sxtw #4]", 12, -4);
-#endif
MEM_TEST("str d17, [x5, x6]", 12, -4);
MEM_TEST("str d17, [x5, x6, lsl #3]", 12, -4);
MEM_TEST("ldrsb w13, [x5,w6,sxtw #0]", 12, 4);
MEM_TEST("ldrsb w13, [x5,w6,sxtw #0]", 12, -4);
-
////////////////////////////////////////////////////////////////
printf("LDR/STR (immediate, SIMD&FP, unsigned offset)\n");
+
MEM_TEST("str q17, [x5, #-32]", 16, 0);
MEM_TEST("str d17, [x5, #-32]", 16, 0);
MEM_TEST("str s17, [x5, #-32]", 16, 0);
-//MEM_TEST("str h17, [x5, #-32]", 16, 0);
-//MEM_TEST("str b17, [x5, #-32]", 16, 0);
+MEM_TEST("str h17, [x5, #-32]", 16, 0);
+MEM_TEST("str b17, [x5, #-32]", 16, 0);
MEM_TEST("ldr q17, [x5, #-32]", 16, 0);
MEM_TEST("ldr d17, [x5, #-32]", 16, 0);
MEM_TEST("ldr s17, [x5, #-32]", 16, 0);
-//MEM_TEST("ldr h17, [x5, #-32]", 16, 0);
-//MEM_TEST("ldr b17, [x5, #-32]", 16, 0);
+MEM_TEST("ldr h17, [x5, #-32]", 16, 0);
+MEM_TEST("ldr b17, [x5, #-32]", 16, 0);
////////////////////////////////////////////////////////////////
printf("LDR/STR (immediate, SIMD&FP, pre/post index)\n");
+
MEM_TEST("str q17, [x5], #-32", 16, 0);
MEM_TEST("str d17, [x5], #-32", 16, 0);
MEM_TEST("str s17, [x5], #-32", 16, 0);
-//MEM_TEST("str h17, [x5], #-32", 16, 0);
-//MEM_TEST("str b17, [x5], #-32", 16, 0);
+MEM_TEST("str h17, [x5], #-32", 16, 0);
+MEM_TEST("str b17, [x5], #-32", 16, 0);
MEM_TEST("ldr q17, [x5], #-32", 16, 0);
MEM_TEST("ldr d17, [x5], #-32", 16, 0);
MEM_TEST("ldr s17, [x5], #-32", 16, 0);
-//MEM_TEST("ldr h17, [x5], #-32", 16, 0);
-//MEM_TEST("ldr b17, [x5], #-32", 16, 0);
+MEM_TEST("ldr h17, [x5], #-32", 16, 0);
+MEM_TEST("ldr b17, [x5], #-32", 16, 0);
MEM_TEST("str q17, [x5, #-32]!", 16, 0);
MEM_TEST("str d17, [x5, #-32]!", 16, 0);
MEM_TEST("str s17, [x5, #-32]!", 16, 0);
-//MEM_TEST("str h17, [x5, #-32]!", 16, 0);
-//MEM_TEST("str b17, [x5, #-32]!", 16, 0);
+MEM_TEST("str h17, [x5, #-32]!", 16, 0);
+MEM_TEST("str b17, [x5, #-32]!", 16, 0);
MEM_TEST("ldr q17, [x5, #-32]!", 16, 0);
MEM_TEST("ldr d17, [x5, #-32]!", 16, 0);
MEM_TEST("ldr s17, [x5, #-32]!", 16, 0);
-//MEM_TEST("ldr h17, [x5, #-32]!", 16, 0);
-//MEM_TEST("ldr b17, [x5, #-32]!", 16, 0);
-
+MEM_TEST("ldr h17, [x5, #-32]!", 16, 0);
+MEM_TEST("ldr b17, [x5, #-32]!", 16, 0);
////////////////////////////////////////////////////////////////
printf("LDUR/STUR (unscaled offset, SIMD&FP)\n");
+
MEM_TEST("str q17, [x5, #-13]", 16, 0);
MEM_TEST("str d17, [x5, #-13]", 16, 0);
MEM_TEST("str s17, [x5, #-13]", 16, 0);
-//MEM_TEST("str h17, [x5, #-13]", 16, 0);
-//MEM_TEST("str b17, [x5, #-13]", 16, 0);
+MEM_TEST("str h17, [x5, #-13]", 16, 0);
+MEM_TEST("str b17, [x5, #-13]", 16, 0);
MEM_TEST("ldr q17, [x5, #-13]", 16, 0);
MEM_TEST("ldr d17, [x5, #-13]", 16, 0);
MEM_TEST("ldr s17, [x5, #-13]", 16, 0);
-//MEM_TEST("ldr h17, [x5, #-13]", 16, 0);
-//MEM_TEST("ldr b17, [x5, #-13]", 16, 0);
+MEM_TEST("ldr h17, [x5, #-13]", 16, 0);
+MEM_TEST("ldr b17, [x5, #-13]", 16, 0);
////////////////////////////////////////////////////////////////
printf("LDR (literal, SIMD&FP) (entirely MISSING)\n");
+MEM_TEST("xyzzy10: ldr s17, xyzzy10 - 8", 0, 0)
+MEM_TEST("xyzzy11: ldr d17, xyzzy11 + 8", 0, 0)
+MEM_TEST("xyzzy12: ldr q17, xyzzy12 + 4", 0, 0)
+
////////////////////////////////////////////////////////////////
-printf("LD1/ST1 (single structure, no offset)\n");
-MEM_TEST("st1 {v17.2d}, [x5]", 3, 0)
-MEM_TEST("st1 {v17.4s}, [x5]", 5, 0)
-MEM_TEST("st1 {v17.8h}, [x5]", 7, 0)
-MEM_TEST("st1 {v17.16b}, [x5]", 13, 0)
-MEM_TEST("st1 {v17.1d}, [x5]", 3, 0)
-MEM_TEST("st1 {v17.2s}, [x5]", 5, 0)
-MEM_TEST("st1 {v17.4h}, [x5]", 7, 0)
-MEM_TEST("st1 {v17.8b}, [x5]", 13, 0)
-
-MEM_TEST("ld1 {v17.2d}, [x5]", 3, 0)
-MEM_TEST("ld1 {v17.4s}, [x5]", 5, 0)
-MEM_TEST("ld1 {v17.8h}, [x5]", 7, 0)
-MEM_TEST("ld1 {v17.16b}, [x5]", 13, 0)
-MEM_TEST("ld1 {v17.1d}, [x5]", 3, 0)
-MEM_TEST("ld1 {v17.2s}, [x5]", 5, 0)
-MEM_TEST("ld1 {v17.4h}, [x5]", 7, 0)
-MEM_TEST("ld1 {v17.8b}, [x5]", 13, 0)
-
-////////////////////////////////////////////////////////////////
-printf("LD1/ST1 (single structure, post index)\n");
-MEM_TEST("st1 {v17.2d}, [x5], #16", 3, 0)
-MEM_TEST("st1 {v17.4s}, [x5], #16", 5, 0)
-MEM_TEST("st1 {v17.8h}, [x5], #16", 7, 0)
-MEM_TEST("st1 {v17.16b}, [x5], #16", 13, 0)
-MEM_TEST("st1 {v17.1d}, [x5], #8", 3, 0)
-MEM_TEST("st1 {v17.2s}, [x5], #8", 5, 0)
-MEM_TEST("st1 {v17.4h}, [x5], #8", 7, 0)
-MEM_TEST("st1 {v17.8b}, [x5], #8", 13, 0)
-
-MEM_TEST("ld1 {v17.2d}, [x5], #16", 3, 0)
-MEM_TEST("ld1 {v17.4s}, [x5], #16", 5, 0)
-MEM_TEST("ld1 {v17.8h}, [x5], #16", 7, 0)
-MEM_TEST("ld1 {v17.16b}, [x5], #16", 13, 0)
-MEM_TEST("ld1 {v17.1d}, [x5], #8", 3, 0)
-MEM_TEST("ld1 {v17.2s}, [x5], #8", 5, 0)
-MEM_TEST("ld1 {v17.4h}, [x5], #8", 7, 0)
-MEM_TEST("ld1 {v17.8b}, [x5], #8", 13, 0)
+printf("LD1/ST1 (multiple 1-elem structs to/from 1 reg\n");
+
+MEM_TEST("st1 {v18.2d}, [x5]", 17, 7)
+MEM_TEST("st1 {v18.2d}, [x5], #16", 9, 9)
+MEM_TEST("st1 {v18.2d}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v18.1d}, [x5]", 17, 7)
+MEM_TEST("st1 {v18.1d}, [x5], #8", 9, 9)
+MEM_TEST("st1 {v18.1d}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v18.4s}, [x5]", 17, 7)
+MEM_TEST("st1 {v18.4s}, [x5], #16", 9, 9)
+MEM_TEST("st1 {v18.4s}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v18.2s}, [x5]", 17, 7)
+MEM_TEST("st1 {v18.2s}, [x5], #8", 9, 9)
+MEM_TEST("st1 {v18.2s}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v18.8h}, [x5]", 17, 7)
+MEM_TEST("st1 {v18.8h}, [x5], #16", 9, 9)
+MEM_TEST("st1 {v18.8h}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v18.4h}, [x5]", 17, 7)
+MEM_TEST("st1 {v18.4h}, [x5], #8", 9, 9)
+MEM_TEST("st1 {v18.4h}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v18.16b}, [x5]", 17, 7)
+MEM_TEST("st1 {v18.16b}, [x5], #16", 9, 9)
+MEM_TEST("st1 {v18.16b}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v18.8b}, [x5]", 17, 7)
+MEM_TEST("st1 {v18.8b}, [x5], #8", 9, 9)
+MEM_TEST("st1 {v18.8b}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v18.2d}, [x5]", 17, 7)
+MEM_TEST("ld1 {v18.2d}, [x5], #16", 9, 9)
+MEM_TEST("ld1 {v18.2d}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v18.1d}, [x5]", 17, 7)
+MEM_TEST("ld1 {v18.1d}, [x5], #8", 9, 9)
+MEM_TEST("ld1 {v18.1d}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v18.4s}, [x5]", 17, 7)
+MEM_TEST("ld1 {v18.4s}, [x5], #16", 9, 9)
+MEM_TEST("ld1 {v18.4s}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v18.2s}, [x5]", 17, 7)
+MEM_TEST("ld1 {v18.2s}, [x5], #8", 9, 9)
+MEM_TEST("ld1 {v18.2s}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v18.8h}, [x5]", 17, 7)
+MEM_TEST("ld1 {v18.8h}, [x5], #16", 9, 9)
+MEM_TEST("ld1 {v18.8h}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v18.4h}, [x5]", 17, 7)
+MEM_TEST("ld1 {v18.4h}, [x5], #8", 9, 9)
+MEM_TEST("ld1 {v18.4h}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v18.16b}, [x5]", 17, 7)
+MEM_TEST("ld1 {v18.16b}, [x5], #16", 9, 9)
+MEM_TEST("ld1 {v18.16b}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v18.8b}, [x5]", 17, 7)
+MEM_TEST("ld1 {v18.8b}, [x5], #8", 9, 9)
+MEM_TEST("ld1 {v18.8b}, [x5], x6", -13, -5)
+
+////////////////////////////////////////////////////////////////
+printf("LD2/ST2 (multiple 2-elem structs to/from 2 regs\n");
+
+MEM_TEST("st2 {v18.2d, v19.2d}, [x5]", 17, 7)
+MEM_TEST("st2 {v18.2d, v19.2d}, [x5], #32", 9, 9)
+MEM_TEST("st2 {v18.2d, v19.2d}, [x5], x6", -13, -5)
+
+/* no 1d case */
+
+MEM_TEST("st2 {v18.4s, v19.4s}, [x5]", 17, 7)
+MEM_TEST("st2 {v18.4s, v19.4s}, [x5], #32", 9, 9)
+MEM_TEST("st2 {v18.4s, v19.4s}, [x5], x6", -13, -5)
+
+MEM_TEST("st2 {v18.2s, v19.2s}, [x5]", 17, 7)
+MEM_TEST("st2 {v18.2s, v19.2s}, [x5], #16", 9, 9)
+MEM_TEST("st2 {v18.2s, v19.2s}, [x5], x6", -13, -5)
+
+MEM_TEST("st2 {v18.8h, v19.8h}, [x5]", 17, 7)
+MEM_TEST("st2 {v18.8h, v19.8h}, [x5], #32", 9, 9)
+MEM_TEST("st2 {v18.8h, v19.8h}, [x5], x6", -13, -5)
+
+MEM_TEST("st2 {v18.4h, v19.4h}, [x5]", 17, 7)
+MEM_TEST("st2 {v18.4h, v19.4h}, [x5], #16", 9, 9)
+MEM_TEST("st2 {v18.4h, v19.4h}, [x5], x6", -13, -5)
+
+MEM_TEST("st2 {v18.16b, v19.16b}, [x5]", 17, 7)
+MEM_TEST("st2 {v18.16b, v19.16b}, [x5], #32", 9, 9)
+MEM_TEST("st2 {v18.16b, v19.16b}, [x5], x6", -13, -5)
+
+MEM_TEST("st2 {v18.8b, v19.8b}, [x5]", 17, 7)
+MEM_TEST("st2 {v18.8b, v19.8b}, [x5], #16", 9, 9)
+MEM_TEST("st2 {v18.8b, v19.8b}, [x5], x6", -13, -5)
+
+MEM_TEST("ld2 {v18.2d, v19.2d}, [x5]", 17, 7)
+MEM_TEST("ld2 {v18.2d, v19.2d}, [x5], #32", 9, 9)
+MEM_TEST("ld2 {v18.2d, v19.2d}, [x5], x6", -13, -5)
+
+/* no 1d case */
+
+MEM_TEST("ld2 {v18.4s, v19.4s}, [x5]", 17, 7)
+MEM_TEST("ld2 {v18.4s, v19.4s}, [x5], #32", 9, 9)
+MEM_TEST("ld2 {v18.4s, v19.4s}, [x5], x6", -13, -5)
+
+MEM_TEST("ld2 {v18.2s, v19.2s}, [x5]", 17, 7)
+MEM_TEST("ld2 {v18.2s, v19.2s}, [x5], #16", 9, 9)
+MEM_TEST("ld2 {v18.2s, v19.2s}, [x5], x6", -13, -5)
+
+MEM_TEST("ld2 {v18.8h, v19.8h}, [x5]", 17, 7)
+MEM_TEST("ld2 {v18.8h, v19.8h}, [x5], #32", 9, 9)
+MEM_TEST("ld2 {v18.8h, v19.8h}, [x5], x6", -13, -5)
+
+MEM_TEST("ld2 {v18.4h, v19.4h}, [x5]", 17, 7)
+MEM_TEST("ld2 {v18.4h, v19.4h}, [x5], #16", 9, 9)
+MEM_TEST("ld2 {v18.4h, v19.4h}, [x5], x6", -13, -5)
+
+MEM_TEST("ld2 {v18.16b, v19.16b}, [x5]", 17, 7)
+MEM_TEST("ld2 {v18.16b, v19.16b}, [x5], #32", 9, 9)
+MEM_TEST("ld2 {v18.16b, v19.16b}, [x5], x6", -13, -5)
+
+MEM_TEST("ld2 {v18.8b, v19.8b}, [x5]", 17, 7)
+MEM_TEST("ld2 {v18.8b, v19.8b}, [x5], #16", 9, 9)
+MEM_TEST("ld2 {v18.8b, v19.8b}, [x5], x6", -13, -5)
+
+////////////////////////////////////////////////////////////////
+printf("LD3/ST3 (multiple 3-elem structs to/from 3 regs\n");
+
+MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
+MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
+MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
+
+/* no 1d case */
+
+MEM_TEST("st3 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
+MEM_TEST("st3 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
+MEM_TEST("st3 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
+
+MEM_TEST("st3 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
+MEM_TEST("st3 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
+MEM_TEST("st3 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
+
+MEM_TEST("st3 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
+MEM_TEST("st3 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
+MEM_TEST("st3 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
+
+MEM_TEST("st3 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
+MEM_TEST("st3 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
+MEM_TEST("st3 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
+
+MEM_TEST("st3 {v17.16b, v18.16b, v19.16b}, [x5]", 17, 7)
+MEM_TEST("st3 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
+MEM_TEST("st3 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
+
+MEM_TEST("st3 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
+MEM_TEST("st3 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
+MEM_TEST("st3 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
+
+MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
+MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
+MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
+
+/* no 1d case */
+
+MEM_TEST("ld3 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
+MEM_TEST("ld3 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
+MEM_TEST("ld3 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
+
+MEM_TEST("ld3 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
+MEM_TEST("ld3 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
+MEM_TEST("ld3 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
+
+MEM_TEST("ld3 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
+MEM_TEST("ld3 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
+MEM_TEST("ld3 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
+
+MEM_TEST("ld3 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
+MEM_TEST("ld3 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
+MEM_TEST("ld3 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
+
+MEM_TEST("ld3 {v17.16b, v18.16b, v19.16b}, [x5]", 17, 7)
+MEM_TEST("ld3 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
+MEM_TEST("ld3 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
+
+MEM_TEST("ld3 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
+MEM_TEST("ld3 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
+MEM_TEST("ld3 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
+
+////////////////////////////////////////////////////////////////
+printf("LD4/ST4 (multiple 4-elem structs to/from 4 regs\n");
+
+MEM_TEST("st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
+MEM_TEST("st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
+MEM_TEST("st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
+
+/* no 1d case */
+
+MEM_TEST("st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
+MEM_TEST("st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
+MEM_TEST("st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
+
+MEM_TEST("st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
+MEM_TEST("st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
+MEM_TEST("st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
+
+MEM_TEST("st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
+MEM_TEST("st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
+MEM_TEST("st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
+
+MEM_TEST("st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
+MEM_TEST("st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
+MEM_TEST("st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
+
+MEM_TEST("st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
+MEM_TEST("st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
+MEM_TEST("st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
+
+MEM_TEST("st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
+MEM_TEST("st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
+MEM_TEST("st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
+
+MEM_TEST("ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
+MEM_TEST("ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
+MEM_TEST("ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
+
+/* no 1d case */
+
+MEM_TEST("ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
+MEM_TEST("ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
+MEM_TEST("ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
+
+MEM_TEST("ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
+MEM_TEST("ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
+MEM_TEST("ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
+
+MEM_TEST("ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
+MEM_TEST("ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
+MEM_TEST("ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
+
+MEM_TEST("ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
+MEM_TEST("ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
+MEM_TEST("ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
+
+MEM_TEST("ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
+MEM_TEST("ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
+MEM_TEST("ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
+
+MEM_TEST("ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
+MEM_TEST("ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
+MEM_TEST("ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
+
+////////////////////////////////////////////////////////////////
+printf("LD1/ST1 (multiple 1-elem structs to/from 2/3/4 regs\n");
+
+//MEM_TEST("st1 {v19.2d, v20.2d}, [x5]", 17, 7)
+//MEM_TEST("st1 {v19.2d, v20.2d}, [x5], #32", 9, 9)
+//MEM_TEST("st1 {v19.2d, v20.2d}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
+//MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
+//MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
+//
+//
+//MEM_TEST("st1 {v19.1d, v20.1d}, [x5]", 17, 7)
+//MEM_TEST("st1 {v19.1d, v20.1d}, [x5], #16", 9, 9)
+//MEM_TEST("st1 {v19.1d, v20.1d}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5], #24", 9, 9)
+//MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], #32", 9, 9)
+//MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], x6", -13, -5)
+//
+//
+//MEM_TEST("st1 {v19.4s, v20.4s}, [x5]", 17, 7)
+//MEM_TEST("st1 {v19.4s, v20.4s}, [x5], #32", 9, 9)
+//MEM_TEST("st1 {v19.4s, v20.4s}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
+//MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
+//MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
+//
+//
+//MEM_TEST("st1 {v19.2s, v20.2s}, [x5]", 17, 7)
+//MEM_TEST("st1 {v19.2s, v20.2s}, [x5], #16", 9, 9)
+//MEM_TEST("st1 {v19.2s, v20.2s}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
+//MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
+//MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
+//
+//
+//MEM_TEST("st1 {v19.8h, v20.8h}, [x5]", 17, 7)
+//MEM_TEST("st1 {v19.8h, v20.8h}, [x5], #32", 9, 9)
+//MEM_TEST("st1 {v19.8h, v20.8h}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
+//MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
+//MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
+//
+//
+//MEM_TEST("st1 {v19.4h, v20.4h}, [x5]", 17, 7)
+//MEM_TEST("st1 {v19.4h, v20.4h}, [x5], #16", 9, 9)
+//MEM_TEST("st1 {v19.4h, v20.4h}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
+//MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
+//MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
+
+
+MEM_TEST("st1 {v19.16b, v20.16b}, [x5]", 17, 7)
+MEM_TEST("st1 {v19.16b, v20.16b}, [x5], #32", 9, 9)
+//MEM_TEST("st1 {v19.16b, v20.16b}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
+//MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
+//MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
+//
+//
+//MEM_TEST("st1 {v19.8b, v20.8b}, [x5]", 17, 7)
+//MEM_TEST("st1 {v19.8b, v20.8b}, [x5], #16", 9, 9)
+//MEM_TEST("st1 {v19.8b, v20.8b}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
+//MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
+//
+//MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
+//MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
+//MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
+//
+//
+//MEM_TEST("ld1 {v19.2d, v20.2d}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.2d, v20.2d}, [x5], #32", 9, 9)
+//MEM_TEST("ld1 {v19.2d, v20.2d}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
+//MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
+//MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
+//
+//
+//MEM_TEST("ld1 {v19.1d, v20.1d}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.1d, v20.1d}, [x5], #16", 9, 9)
+//MEM_TEST("ld1 {v19.1d, v20.1d}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5], #24", 9, 9)
+//MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], #32", 9, 9)
+//MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], x6", -13, -5)
+//
+//
+//MEM_TEST("ld1 {v19.4s, v20.4s}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.4s, v20.4s}, [x5], #32", 9, 9)
+//MEM_TEST("ld1 {v19.4s, v20.4s}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
+//MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
+//MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
+//
+//
+//MEM_TEST("ld1 {v19.2s, v20.2s}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.2s, v20.2s}, [x5], #16", 9, 9)
+//MEM_TEST("ld1 {v19.2s, v20.2s}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
+//MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
+//MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
+//
+//
+//MEM_TEST("ld1 {v19.8h, v20.8h}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.8h, v20.8h}, [x5], #32", 9, 9)
+//MEM_TEST("ld1 {v19.8h, v20.8h}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
+//MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
+//MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
+//
+//
+//MEM_TEST("ld1 {v19.4h, v20.4h}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.4h, v20.4h}, [x5], #16", 9, 9)
+//MEM_TEST("ld1 {v19.4h, v20.4h}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
+//MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
+//MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
+
+
+MEM_TEST("ld1 {v19.16b, v20.16b}, [x5]", 17, 7)
+MEM_TEST("ld1 {v19.16b, v20.16b}, [x5], #32", 9, 9)
+//MEM_TEST("ld1 {v19.16b, v20.16b}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
+//MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
+//MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
+//
+//
+//MEM_TEST("ld1 {v19.8b, v20.8b}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.8b, v20.8b}, [x5], #16", 9, 9)
+//MEM_TEST("ld1 {v19.8b, v20.8b}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
+//MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
+//
+//MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
+//MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
+//MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
+
////////////////////////////////////////////////////////////////
printf("LD1R (single structure, replicate)\n");
+
MEM_TEST("ld1r {v17.2d}, [x5]", 3, -5)
MEM_TEST("ld1r {v17.1d}, [x5]", 3, -4)
MEM_TEST("ld1r {v17.4s}, [x5]", 3, -3)
MEM_TEST("ld1r {v17.16b}, [x5], x6", 3, 2)
MEM_TEST("ld1r {v17.8b}, [x5], x6", 3, 3)
+
////////////////////////////////////////////////////////////////
-printf("LD2/ST2 (multiple 2-elem structs to/from 2/regs, post index)"
- " (VERY INCOMPLETE)\n");
+printf("LD2R (single structure, replicate)\n");
+
+//MEM_TEST("ld2r {v17.2d , v18.2d }, [x5]", 3, -5)
+//MEM_TEST("ld2r {v18.1d , v19.1d }, [x5]", 3, -4)
+//MEM_TEST("ld2r {v19.4s , v20.4s }, [x5]", 3, -3)
+//MEM_TEST("ld2r {v17.2s , v18.2s }, [x5]", 3, -2)
+//MEM_TEST("ld2r {v18.8h , v19.8h }, [x5]", 3, -1)
+//MEM_TEST("ld2r {v19.4h , v20.4h }, [x5]", 3, 1)
+//MEM_TEST("ld2r {v17.16b, v18.16b}, [x5]", 3, 2)
+//MEM_TEST("ld2r {v18.8b , v19.8b }, [x5]", 3, 3)
+//
+//MEM_TEST("ld2r {v19.2d , v20.2d }, [x5], #16", 3, -5)
+//MEM_TEST("ld2r {v17.1d , v18.1d }, [x5], #16", 3, -4)
+//MEM_TEST("ld2r {v18.4s , v19.4s }, [x5], #8", 3, -3)
+//MEM_TEST("ld2r {v19.2s , v20.2s }, [x5], #8", 3, -2)
+//MEM_TEST("ld2r {v17.8h , v18.8h }, [x5], #4", 3, -1)
+//MEM_TEST("ld2r {v18.4h , v19.4h }, [x5], #4", 3, 1)
+//MEM_TEST("ld2r {v19.16b, v20.16b}, [x5], #2", 3, 2)
+//MEM_TEST("ld2r {v17.8b , v18.8b }, [x5], #2", 3, 3)
+//
+//MEM_TEST("ld2r {v18.2d , v19.2d }, [x5], x6", 3, -5)
+//MEM_TEST("ld2r {v19.1d , v20.1d }, [x5], x6", 3, -4)
+//MEM_TEST("ld2r {v17.4s , v18.4s }, [x5], x6", 3, -3)
+//MEM_TEST("ld2r {v18.2s , v19.2s }, [x5], x6", 3, -2)
+//MEM_TEST("ld2r {v19.8h , v20.8h }, [x5], x6", 3, -1)
+//MEM_TEST("ld2r {v17.4h , v18.4h }, [x5], x6", 3, 1)
+//MEM_TEST("ld2r {v18.16b, v19.16b}, [x5], x6", 3, 2)
+//MEM_TEST("ld2r {v19.8b , v20.8b }, [x5], x6", 3, 3)
+
+
+//////////////////////////////////////////////////////////////////
+//printf("LD3R (single structure, replicate)\n");
+
+//MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5]", 3, -5)
+//MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5]", 3, -4)
+//MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5]", 3, -3)
+//MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5]", 3, -2)
+//MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5]", 3, -5)
+//MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5]", 3, -4)
+//MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5]", 3, -3)
+//MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5]", 3, -2)
+//
+//MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5], #24", 3, -5)
+//MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5], #24", 3, -4)
+//MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5], #12", 3, -3)
+//MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5], #12", 3, -2)
+//MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5], #6", 3, -5)
+//MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5], #6", 3, -4)
+//MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5], #3", 3, -3)
+//MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5], #3", 3, -2)
+//
+//MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5], x6", 3, -5)
+//MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5], x6", 3, -4)
+//MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5], x6", 3, -3)
+//MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5], x6", 3, -2)
+//MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5], x6", 3, -5)
+//MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5], x6", 3, -4)
+//MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5], x6", 3, -3)
+//MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5], x6", 3, -2)
-MEM_TEST("ld2 {v17.2d, v18.2d}, [x5], #32", 3, 0)
-MEM_TEST("st2 {v17.2d, v18.2d}, [x5], #32", 7, 0)
-MEM_TEST("ld2 {v17.4s, v18.4s}, [x5], #32", 13, 0)
-MEM_TEST("st2 {v17.4s, v18.4s}, [x5], #32", 17, 0)
+////////////////////////////////////////////////////////////////
+printf("LD4R (single structure, replicate)\n");
+
+//MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5]", 3, -5)
+//MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5]", 3, -4)
+//MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5]", 3, -3)
+//MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5]", 3, -2)
+//MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5]", 3, -5)
+//MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5]", 3, -4)
+//MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 3, -3)
+//MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5]", 3, -2)
+//
+//MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5], #32", 3, -5)
+//MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5], #32", 3, -4)
+//MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5], #16", 3, -3)
+//MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5], #16", 3, -2)
+//MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5], #8", 3, -5)
+//MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5], #8", 3, -4)
+//MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #4", 3, -3)
+//MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5], #4", 3, -2)
+//
+//MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5], x6", 3, -5)
+//MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5], x6", 3, -4)
+//MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5], x6", 3, -3)
+//MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5], x6", 3, -2)
+//MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5], x6", 3, -5)
+//MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5], x6", 3, -4)
+//MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", 3, -3)
+//MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5], x6", 3, -2)
////////////////////////////////////////////////////////////////
-printf("LD1/ST1 (multiple 1-elem structs to/from 2 regs, no offset)"
- " (VERY INCOMPLETE)\n");
+printf("LD1/ST1 (single 1-elem struct to/from one lane of 1 reg\n");
-MEM_TEST("ld1 {v17.16b, v18.16b}, [x5]", 3, 0)
-MEM_TEST("st1 {v17.16b, v18.16b}, [x5]", 7, 0)
+//MEM_TEST("st1 {v19.d}[0], [x5]", 17, 7)
+//MEM_TEST("st1 {v19.d}[0], [x5], #8", -9, 12)
+//MEM_TEST("st1 {v19.d}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st1 {v19.d}[1], [x5]", 17, 7)
+//MEM_TEST("st1 {v19.d}[1], [x5], #8", -9, 12)
+//MEM_TEST("st1 {v19.d}[1], [x5], x6", 9, 13)
+//
+//MEM_TEST("st1 {v19.s}[0], [x5]", 17, 7)
+//MEM_TEST("st1 {v19.s}[0], [x5], #4", -9, 12)
+//MEM_TEST("st1 {v19.s}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st1 {v19.s}[3], [x5]", 17, 7)
+//MEM_TEST("st1 {v19.s}[3], [x5], #4", -9, 12)
+//MEM_TEST("st1 {v19.s}[3], [x5], x6", 9, 13)
+//
+//MEM_TEST("st1 {v19.h}[0], [x5]", 17, 7)
+//MEM_TEST("st1 {v19.h}[0], [x5], #2", -9, 12)
+//MEM_TEST("st1 {v19.h}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st1 {v19.h}[6], [x5]", 17, 7)
+//MEM_TEST("st1 {v19.h}[6], [x5], #2", -9, 12)
+//MEM_TEST("st1 {v19.h}[6], [x5], x6", 9, 13)
+//
+//MEM_TEST("st1 {v19.b}[0], [x5]", 17, 7)
+//MEM_TEST("st1 {v19.b}[0], [x5], #1", -9, 12)
+//MEM_TEST("st1 {v19.b}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st1 {v19.b}[13], [x5]", 17, 7)
+//MEM_TEST("st1 {v19.b}[13], [x5], #1", -9, 12)
+//MEM_TEST("st1 {v19.b}[13], [x5], x6", 9, 13)
+//
+//
+//MEM_TEST("ld1 {v19.d}[0], [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.d}[0], [x5], #8", -9, 12)
+//MEM_TEST("ld1 {v19.d}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld1 {v19.d}[1], [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.d}[1], [x5], #8", -9, 12)
+//MEM_TEST("ld1 {v19.d}[1], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld1 {v19.s}[0], [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.s}[0], [x5], #4", -9, 12)
+//MEM_TEST("ld1 {v19.s}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld1 {v19.s}[3], [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.s}[3], [x5], #4", -9, 12)
+//MEM_TEST("ld1 {v19.s}[3], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld1 {v19.h}[0], [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.h}[0], [x5], #2", -9, 12)
+//MEM_TEST("ld1 {v19.h}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld1 {v19.h}[6], [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.h}[6], [x5], #2", -9, 12)
+//MEM_TEST("ld1 {v19.h}[6], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld1 {v19.b}[0], [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.b}[0], [x5], #1", -9, 12)
+//MEM_TEST("ld1 {v19.b}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld1 {v19.b}[13], [x5]", 17, 7)
+//MEM_TEST("ld1 {v19.b}[13], [x5], #1", -9, 12)
+//MEM_TEST("ld1 {v19.b}[13], [x5], x6", 9, 13)
////////////////////////////////////////////////////////////////
-printf("LD1/ST1 (multiple 1-elem structs to/from 2 regs, post index)"
- " (VERY INCOMPLETE)\n");
+printf("LD2/ST2 (single 2-elem struct to/from one lane of 2 regs\n");
-MEM_TEST("ld1 {v17.16b, v18.16b}, [x5], #32", 3, 0)
-MEM_TEST("st1 {v17.16b, v18.16b}, [x5], #32", 7, 0)
+//MEM_TEST("st2 {v18.d, v19.d}[0], [x5]", 17, 7)
+//MEM_TEST("st2 {v18.d, v19.d}[0], [x5], #16", -9, 12)
+//MEM_TEST("st2 {v18.d, v19.d}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st2 {v18.d, v19.d}[1], [x5]", 17, 7)
+//MEM_TEST("st2 {v18.d, v19.d}[1], [x5], #16", -9, 12)
+//MEM_TEST("st2 {v18.d, v19.d}[1], [x5], x6", 9, 13)
+//
+//MEM_TEST("st2 {v18.s, v19.s}[0], [x5]", 17, 7)
+//MEM_TEST("st2 {v18.s, v19.s}[0], [x5], #8", -9, 12)
+//MEM_TEST("st2 {v18.s, v19.s}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st2 {v18.s, v19.s}[3], [x5]", 17, 7)
+//MEM_TEST("st2 {v18.s, v19.s}[3], [x5], #8", -9, 12)
+//MEM_TEST("st2 {v18.s, v19.s}[3], [x5], x6", 9, 13)
+//
+//MEM_TEST("st2 {v18.h, v19.h}[0], [x5]", 17, 7)
+//MEM_TEST("st2 {v18.h, v19.h}[0], [x5], #4", -9, 12)
+//MEM_TEST("st2 {v18.h, v19.h}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st2 {v18.h, v19.h}[6], [x5]", 17, 7)
+//MEM_TEST("st2 {v18.h, v19.h}[6], [x5], #4", -9, 12)
+//MEM_TEST("st2 {v18.h, v19.h}[6], [x5], x6", 9, 13)
+//
+//MEM_TEST("st2 {v18.b, v19.b}[0], [x5]", 17, 7)
+//MEM_TEST("st2 {v18.b, v19.b}[0], [x5], #2", -9, 12)
+//MEM_TEST("st2 {v18.b, v19.b}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st2 {v18.b, v19.b}[13], [x5]", 17, 7)
+//MEM_TEST("st2 {v18.b, v19.b}[13], [x5], #2", -9, 12)
+//MEM_TEST("st2 {v18.b, v19.b}[13], [x5], x6", 9, 13)
+//
+//
+//MEM_TEST("ld2 {v18.d, v19.d}[0], [x5]", 17, 7)
+//MEM_TEST("ld2 {v18.d, v19.d}[0], [x5], #16", -9, 12)
+//MEM_TEST("ld2 {v18.d, v19.d}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld2 {v18.d, v19.d}[1], [x5]", 17, 7)
+//MEM_TEST("ld2 {v18.d, v19.d}[1], [x5], #16", -9, 12)
+//MEM_TEST("ld2 {v18.d, v19.d}[1], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld2 {v18.s, v19.s}[0], [x5]", 17, 7)
+//MEM_TEST("ld2 {v18.s, v19.s}[0], [x5], #8", -9, 12)
+//MEM_TEST("ld2 {v18.s, v19.s}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld2 {v18.s, v19.s}[3], [x5]", 17, 7)
+//MEM_TEST("ld2 {v18.s, v19.s}[3], [x5], #8", -9, 12)
+//MEM_TEST("ld2 {v18.s, v19.s}[3], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld2 {v18.h, v19.h}[0], [x5]", 17, 7)
+//MEM_TEST("ld2 {v18.h, v19.h}[0], [x5], #4", -9, 12)
+//MEM_TEST("ld2 {v18.h, v19.h}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld2 {v18.h, v19.h}[6], [x5]", 17, 7)
+//MEM_TEST("ld2 {v18.h, v19.h}[6], [x5], #4", -9, 12)
+//MEM_TEST("ld2 {v18.h, v19.h}[6], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld2 {v18.b, v19.b}[0], [x5]", 17, 7)
+//MEM_TEST("ld2 {v18.b, v19.b}[0], [x5], #2", -9, 12)
+//MEM_TEST("ld2 {v18.b, v19.b}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld2 {v18.b, v19.b}[13], [x5]", 17, 7)
+//MEM_TEST("ld2 {v18.b, v19.b}[13], [x5], #2", -9, 12)
+//MEM_TEST("ld2 {v18.b, v19.b}[13], [x5], x6", 9, 13)
////////////////////////////////////////////////////////////////
-printf("LD1/ST1 (multiple 1-elem structs to/from 3 regs, no offset)"
- " (VERY INCOMPLETE)\n");
+printf("LD3/ST3 (single 3-elem struct to/from one lane of 3 regs\n");
-MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5]", 3, 0)
-MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5]", 7, 0)
+//MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5]", 17, 7)
+//MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5], #24", -9, 12)
+//MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5]", 17, 7)
+//MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5], #24", -9, 12)
+//MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5], x6", 9, 13)
+//
+//MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5]", 17, 7)
+//MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5], #12", -9, 12)
+//MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5]", 17, 7)
+//MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5], #12", -9, 12)
+//MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5], x6", 9, 13)
+//
+//MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5]", 17, 7)
+//MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5], #6", -9, 12)
+//MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5]", 17, 7)
+//MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5], #6", -9, 12)
+//MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5], x6", 9, 13)
+//
+//MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5]", 17, 7)
+//MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5], #3", -9, 12)
+//MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5]", 17, 7)
+//MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5], #3", -9, 12)
+//MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5], x6", 9, 13)
+//
+//
+//MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5]", 17, 7)
+//MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5], #24", -9, 12)
+//MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5]", 17, 7)
+//MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5], #24", -9, 12)
+//MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5]", 17, 7)
+//MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5], #12", -9, 12)
+//MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5]", 17, 7)
+//MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5], #12", -9, 12)
+//MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5]", 17, 7)
+//MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5], #6", -9, 12)
+//MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5]", 17, 7)
+//MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5], #6", -9, 12)
+//MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5]", 17, 7)
+//MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5], #3", -9, 12)
+//MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5]", 17, 7)
+//MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5], #3", -9, 12)
+//MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5], x6", 9, 13)
////////////////////////////////////////////////////////////////
-printf("LD3/ST3 (multiple 3-elem structs to/from 3/regs, post index)"
- " (VERY INCOMPLETE)\n");
-
-MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5], #48", 13, 0)
-MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5], #48", 17, 0)
-
+printf("LD4/ST4 (single 4-elem struct to/from one lane of 4 regs\n");
+//MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5]", 17, 7)
+//MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], #32", -9, 12)
+//MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5]", 17, 7)
+//MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], #32", -9, 12)
+//MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], x6", 9, 13)
+//
+//MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5]", 17, 7)
+//MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], #16", -9, 12)
+//MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5]", 17, 7)
+//MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], #16", -9, 12)
+//MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], x6", 9, 13)
+//
+//MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5]", 17, 7)
+//MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], #8", -9, 12)
+//MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5]", 17, 7)
+//MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], #8", -9, 12)
+//MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], x6", 9, 13)
+//
+//MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5]", 17, 7)
+//MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], #4", -9, 12)
+//MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5]", 17, 7)
+//MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], #4", -9, 12)
+//MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], x6", 9, 13)
+//
+//
+//MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5]", 17, 7)
+//MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], #32", -9, 12)
+//MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5]", 17, 7)
+//MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], #32", -9, 12)
+//MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5]", 17, 7)
+//MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], #16", -9, 12)
+//MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5]", 17, 7)
+//MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], #16", -9, 12)
+//MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5]", 17, 7)
+//MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], #8", -9, 12)
+//MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5]", 17, 7)
+//MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], #8", -9, 12)
+//MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5]", 17, 7)
+//MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], #4", -9, 12)
+//MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], x6", 9, 13)
+//
+//MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5]", 17, 7)
+//MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], #4", -9, 12)
+//MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], x6", 9, 13)
} /* end of test_memory2() */
int main ( void )
{
- if (1) test_memory();
- if (1) test_memory2();
+ if (1) test_memory_old();
+ if (1) test_memory_new();
return 0;
}
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-LDR (literal, int reg) (DONE ABOVE)
-{LD,ST}R (integer register) (entirely MISSING)
+LDR (literal, int reg) (done above by test_memory_old)
+{LD,ST}R (integer register)
str x13, [x5, x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-LDRS{B,H,W} (simm9, upd) (upd check is MISSING)
+LDRS{B,H,W} (simm9, upd)
ldrsw x13, [x5, #-24]! with x5 = middle_of_block+-16, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x6 (sub, index reg)
LDP,STP (immediate, simm7) (FP&VEC)
-stp q17, q18, [x5, 32] with x5 = middle_of_block+-16, x6=4
+stp q17, q18, [x5, 16] with x5 = middle_of_block+-15, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 55 18 f1 5c aa 84 c0 38 cd 7e 31 c8 92 f4 b0 e7
- [160] 0e 6c 4b d1 1e 2a 76 4c e2 a7 c8 5a 26 59 0e 5b
+ [128] .. bd 4c a2 27 58 b6 cf 33 b0 ec 02 4e cc f7 5d
+ [144] 81 6f 2c 5d 12 32 3e 5e d7 fe 1c a2 88 01 9f 33
+ [160] 10 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-stp q17, q18, [x5, 32]! with x5 = middle_of_block+-16, x6=4
+stp q19, q18, [x5, 32]! with x5 = middle_of_block+-11, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 02 3e c1 07 ca e4 d0 ed 19 98 1e 29 25 e0 75 25
- [160] e1 0f a7 69 a1 4c 5b 2c 01 08 48 ca f8 ff dc 16
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. f6 6f 1e 81 d6 09 02 1b d1 46 55
+ [160] 8c 95 04 fe d9 a0 72 a8 70 85 36 45 34 12 90 c2
+ [176] 38 61 c9 6d 5a .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
32 x5 (sub, base reg)
0 x6 (sub, index reg)
-stp q17, q18, [x5], 32 with x5 = middle_of_block+-16, x6=4
+stp q20, q17, [x5], -48 with x5 = middle_of_block+-7, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 67 98 a3 78 5f 8e f9 57 5e 90 fc 32 c8 db d6 2c
- [128] 20 68 2a 31 1b f7 e9 b2 9f 6a 21 20 db 21 17 27
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. a2 41 aa 2b 45 8f 49
+ [128] 40 cb 2f 6e 6f ad 6d dc bf 7b fc 5a 14 1b 6f d2
+ [144] e9 bf cc d2 e1 68 5b 88 c9 .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
+ -48 x5 (sub, base reg)
0 x6 (sub, index reg)
-stp d17, d18, [x5, 32] with x5 = middle_of_block+-16, x6=4
+stp d18, d17, [x5, 16] with x5 = middle_of_block+-15, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] a0 6c d2 7f 89 d1 b1 b6 c5 5d 74 11 63 9d cb b9
+ [128] .. 16 31 7c 68 e5 76 f9 30 7b 9d e8 08 b7 66 71
+ [144] 7e .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-stp d17, d18, [x5, 32]! with x5 = middle_of_block+-16, x6=4
+stp d17, d19, [x5, 32]! with x5 = middle_of_block+-11, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 6f 14 75 6c 06 fe e1 ea 40 30 6e 55 7c 36 4d c4
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. c3 f0 f2 4b b4 31 3e 1a 81 56 08
+ [160] d0 18 fd a8 ee .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
32 x5 (sub, base reg)
0 x6 (sub, index reg)
-stp d17, d18, [x5], 32 with x5 = middle_of_block+-16, x6=4
+stp d20, d18, [x5], -48 with x5 = middle_of_block+-7, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] c2 ae 80 3d 80 4f 9f 9e 93 76 25 55 85 51 97 1a
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. 0a 9c c9 d7 ad 2c 37
+ [128] 86 b9 a7 1f 66 8d 68 37 e2 .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
+ -48 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldp q17, q18, [x5, 32] with x5 = middle_of_block+-16, x6=4
+stp s17, s18, [x5, 16] with x5 = middle_of_block+-15, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. 62 fd 3c be d8 63 15 74 .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- c3aeec76faa5f5c3 v17.d[0] (xor, xfer vecreg #1)
- d81dc8f6818b6e41 v17.d[1] (xor, xfer vecreg #1)
- c4709239d600ee90 v18.d[0] (xor, xfer vecreg #2)
- a640a2efa8725362 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldp q17, q18, [x5, 32]! with x5 = middle_of_block+-16, x6=4
+stp s19, s18, [x5, 32]! with x5 = middle_of_block+-11, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. 14 3b 0c b2 bd 82 48 0e .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 80b42ff8dc0573ed v17.d[0] (xor, xfer vecreg #1)
- 978d0461007b54b8 v17.d[1] (xor, xfer vecreg #1)
- 47b1ef6f289cbd69 v18.d[0] (xor, xfer vecreg #2)
- 4283a680f9f42f27 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
32 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldp q17, q18, [x5], 32 with x5 = middle_of_block+-16, x6=4
+stp s20, s17, [x5], -48 with x5 = middle_of_block+-7, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. f0 e1 6f b0 c7 a1
+ [128] c7 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 32e4abace36584a4 v17.d[0] (xor, xfer vecreg #1)
- 94465539af6bee2a v17.d[1] (xor, xfer vecreg #1)
- 45ee7595ed87a70a v18.d[0] (xor, xfer vecreg #2)
- 0b0689e9f49030da v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
+ -48 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldp d17, d18, [x5, 32] with x5 = middle_of_block+-16, x6=4
+ldp q17, q18, [x5, 16] with x5 = middle_of_block+-15, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 81468c3a81e28308 v17.d[0] (xor, xfer vecreg #1)
- 9402389a9fd7e622 v17.d[1] (xor, xfer vecreg #1)
- ac80e445d56aaf23 v18.d[0] (xor, xfer vecreg #2)
- f429df6f28a16e8a v18.d[1] (xor, xfer vecreg #2)
+ fd4d95acd1d6d139 v17.d[0] (xor, xfer vecreg #1)
+ 9dc81cb46d6f9e7f v17.d[1] (xor, xfer vecreg #1)
+ 63e4be3e036ae755 v18.d[0] (xor, xfer vecreg #2)
+ ad6fc21a5484bfd8 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldp d17, d18, [x5, 32]! with x5 = middle_of_block+-16, x6=4
+ldp q18, q19, [x5, 32]! with x5 = middle_of_block+-11, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 63c656d72c05e674 v17.d[0] (xor, xfer vecreg #1)
- 0693fb5daf24d9a0 v17.d[1] (xor, xfer vecreg #1)
- ce871ca48d1a40cc v18.d[0] (xor, xfer vecreg #2)
- d38bf1af25daca31 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 2efef1c6cb5972fd v18.d[0] (xor, xfer vecreg #2)
+ 9da4185695d7e8e5 v18.d[1] (xor, xfer vecreg #2)
+ e25c4c7939011038 v19.d[0] (xor, xfer vecreg #3)
+ 43369059a19bef16 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
32 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldp d17, d18, [x5], 32 with x5 = middle_of_block+-16, x6=4
+ldp q19, q20, [x5], -48 with x5 = middle_of_block+-7, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- ce2bf285733f1da6 v17.d[0] (xor, xfer vecreg #1)
- d57bc365125181f6 v17.d[1] (xor, xfer vecreg #1)
- 0fde67d4c6716a14 v18.d[0] (xor, xfer vecreg #2)
- f4335fd1bac1932e v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 380867a2b26c5ae9 v19.d[0] (xor, xfer vecreg #3)
+ 84e73db11e0e0988 v19.d[1] (xor, xfer vecreg #3)
+ 95c99a138db8a14c v20.d[0] (xor, xfer vecreg #3)
+ 174ba86c16e0412c v20.d[1] (xor, xfer vecreg #3)
+ -48 x5 (sub, base reg)
0 x6 (sub, index reg)
-{LD,ST}R (vector register)
-str d17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ldp d20, d17, [x5, 16] with x5 = middle_of_block+-15, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. db 63 b8 ac e6 bd 2f 97
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 6c022f73599d72b7 v17.d[0] (xor, xfer vecreg #1)
+ 45b073c64b910378 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ b04a728a4c36c5e2 v20.d[0] (xor, xfer vecreg #3)
+ ec29d59640307df2 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str d17, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4
+ldp d17, d18, [x5, 32]! with x5 = middle_of_block+-11, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. 0e cf b0 95
- [112] ba ca a7 9c .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 73ecae0345d336a8 v17.d[0] (xor, xfer vecreg #1)
+ 9a25ef93df18847a v17.d[1] (xor, xfer vecreg #1)
+ 1dabe7985217ffdf v18.d[0] (xor, xfer vecreg #2)
+ 0f24d90dbe67f87b v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
+ 32 x5 (sub, base reg)
0 x6 (sub, index reg)
-str d17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ldp d18, d19, [x5], -48 with x5 = middle_of_block+-7, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 20 05 ac 34 8e ff 78 7a .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 217dc686c9837fd2 v18.d[0] (xor, xfer vecreg #2)
+ 9156af4f348edd73 v18.d[1] (xor, xfer vecreg #2)
+ 1b69a2b04f690fe0 v19.d[0] (xor, xfer vecreg #3)
+ 1b248b9851b82d7c v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
+ -48 x5 (sub, base reg)
0 x6 (sub, index reg)
-str d17, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4
+ldp s19, s20, [x5, 16] with x5 = middle_of_block+-15, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. 61 1e 17 07
- [176] cd a0 14 3e .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 55912fccff3122a8 v19.d[0] (xor, xfer vecreg #3)
+ f388894c63445736 v19.d[1] (xor, xfer vecreg #3)
+ 3c4c9a77caf5f3b6 v20.d[0] (xor, xfer vecreg #3)
+ f0f5b17e7390f59a v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str d17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ldp s20, s17, [x5, 32]! with x5 = middle_of_block+-11, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] fe 3c 6b 02 b7 fe 10 c3 .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 2cc96c1caeac325b v17.d[0] (xor, xfer vecreg #1)
+ 9d8b1950df6462ca v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
+ 333e641331c49978 v20.d[0] (xor, xfer vecreg #3)
+ 08bf6a619a0605a4 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
0 x6 (sub, index reg)
-str d17, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4
+ldp s17, s18, [x5], -48 with x5 = middle_of_block+-7, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. 7f b8 e7 ca
- [112] 50 fb 04 68 .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 37b6725a7bfe8dad v17.d[0] (xor, xfer vecreg #1)
+ 2d88b09804114315 v17.d[1] (xor, xfer vecreg #1)
+ 0fa51cfe6f35ad82 v18.d[0] (xor, xfer vecreg #2)
+ 173f3e9699c5048f v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
+ -48 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr d17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+LDNP,STNP (immediate, simm7) (FP&VEC, w/ nontemporal hint)
+stnp q18, q17, [x5, 16] with x5 = middle_of_block+-15, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. ac f7 6b bd cf 03 b0 83 c0 0c 6c d0 aa 77 21
+ [144] e1 5b 8d a5 c6 ed b2 1f c5 a4 57 80 7c dc 6f f4
+ [160] 7c .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 368c5b732c1248a5 v17.d[0] (xor, xfer vecreg #1)
- f68888b1170ad684 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr d17, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4
+stnp d20, d19, [x5, 40] with x5 = middle_of_block+-15, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. d0 29 f0 b5 e3 db a6
+ [160] 8a c9 9b 24 7a 97 25 d8 38 .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- ee01fe34a2d85c41 v17.d[0] (xor, xfer vecreg #1)
- 3b8184af9c823f6c v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr d17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+stnp s19, s18, [x5, 68] with x5 = middle_of_block+-15, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. 5d 4f 97 f2 77 26 3b 92 .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- dc4fd084ba3953c1 v17.d[0] (xor, xfer vecreg #1)
- 426589a518aea21f v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr d17, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4
+ldnp q18, q17, [x5, 16] with x5 = middle_of_block+-15, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 619304aa5a129766 v17.d[0] (xor, xfer vecreg #1)
- 4e2a7aa80ec124f3 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 1863e40e9f05a130 v17.d[0] (xor, xfer vecreg #1)
+ fd8da7f4047d4a5c v17.d[1] (xor, xfer vecreg #1)
+ 9c71f3b5951b44fc v18.d[0] (xor, xfer vecreg #2)
+ 57052049100404e8 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr d17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ldnp d17, d20, [x5, 40] with x5 = middle_of_block+-15, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 8d7d6fe89f4f3dd9 v17.d[0] (xor, xfer vecreg #1)
+ 1220e3b71285fdad v17.d[0] (xor, xfer vecreg #1)
a2c23ccc03f0e73c v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 3aaead59d2783834 v20.d[0] (xor, xfer vecreg #3)
+ 0d3c304b040245f2 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr d17, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4
+ldnp s20, s19, [x5, 68] with x5 = middle_of_block+-15, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 480d291c1baa1e67 v17.d[0] (xor, xfer vecreg #1)
- 8323b3257a6e114c v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ c16cf1011552cae6 v19.d[0] (xor, xfer vecreg #3)
+ 919474a659a09380 v19.d[1] (xor, xfer vecreg #3)
+ 3ed22f5016357402 v20.d[0] (xor, xfer vecreg #3)
+ c880b37125c69a67 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str s17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+{LD,ST}R (vector register)
+str q17, [x5, x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. 05 44 01 d5 .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. 05 44 01 d5 a9 6c 4a 4c
+ [144] c3 a4 b0 8c 71 29 81 59 .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str s17, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4
+str q17, [x5, x6, lsl #4] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. 3c 31 df 65
+ [ 80] c2 05 e4 42 47 76 bc 1c bf b1 09 4c .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. 5b 32 ec e5
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str s17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+str q17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 79 ee 29 c6 .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 79 ee 29 c6 43 78 e6 88 5b 65 78 d3 9d ea d6 de
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str s17, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4
+str q17, [x5, w6, uxtw #4] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. 41 e4 eb 1d
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. a2 51 33 22
+ [208] 32 c4 8c 62 5b e4 70 75 f2 0d 29 99 .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str s17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+str q17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] e6 b1 03 2d .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] e6 b1 03 2d d2 5c f2 41 0a 9c 62 02 b3 0f bc a6
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str s17, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4
+str q17, [x5, w6, sxtw #4] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. 5b b6 0f 06
+ [ 80] d4 47 39 61 60 c4 0c cb 4e f0 d2 5c .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. ec f6 d1 82
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr s17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ldr q17, [x5, x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- f1bb54fe78f0286a v17.d[0] (xor, xfer vecreg #1)
- 63b582e54ba32e35 v17.d[1] (xor, xfer vecreg #1)
+ 3a1f34b078f0286a v17.d[0] (xor, xfer vecreg #1)
+ 0ad552e36bbe546b v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr s17, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4
+ldr q17, [x5, x6, lsl #4] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 59faf450fdf6566e v17.d[0] (xor, xfer vecreg #1)
- 3ba5adb465ed9857 v17.d[1] (xor, xfer vecreg #1)
+ d9d80c05a86cb0d4 v17.d[0] (xor, xfer vecreg #1)
+ 45fd8dfee4ba7a48 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr s17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ldr q17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- cfed330c080743c7 v17.d[0] (xor, xfer vecreg #1)
- 03f1916ba55aac35 v17.d[1] (xor, xfer vecreg #1)
+ b383b87d080743c7 v17.d[0] (xor, xfer vecreg #1)
+ c2577edb8650a2a1 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr s17, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4
+ldr q17, [x5, w6, uxtw #4] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 160a73c656d57e46 v17.d[0] (xor, xfer vecreg #1)
- 018e121e8f1f8f24 v17.d[1] (xor, xfer vecreg #1)
+ 79368f7f511fde88 v17.d[0] (xor, xfer vecreg #1)
+ aa443df1996f21cb v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr s17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ldr q17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- f4c4181184dc39c4 v17.d[0] (xor, xfer vecreg #1)
- 776e13e3a8706377 v17.d[1] (xor, xfer vecreg #1)
+ a70c9f6884dc39c4 v17.d[0] (xor, xfer vecreg #1)
+ f25c8a41daf6300b v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr s17, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4
+ldr q17, [x5, w6, sxtw #4] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 2c8e878293ad5852 v17.d[0] (xor, xfer vecreg #1)
- ab8679cc737f4e82 v17.d[1] (xor, xfer vecreg #1)
+ e21438395dfcd17a v17.d[0] (xor, xfer vecreg #1)
+ 50f742bad0edaecc v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str h17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+str d17, [x5, x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. d9 84 .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. d9 84 bc 23 26 89 e9 36
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str h17, [x5, x6, lsl #1] with x5 = middle_of_block+12, x6=-4
+str d17, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. a9 98 .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. 60 02 e0 c6
+ [112] d9 93 b3 4b .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str h17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+str d17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 2c 25 .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 2c 25 49 ef 62 4f 07 3c .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str h17, [x5, w6, uxtw #1] with x5 = middle_of_block+12, x6=4
+str d17, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. c3 7f .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. 0a e6 13 11
+ [176] 0b e7 74 6f .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str h17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+str d17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 28 75 .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 28 75 3e ef 58 19 85 66 .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str h17, [x5, w6, sxtw #1] with x5 = middle_of_block+12, x6=-4
+str d17, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. 92 d2 .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. 7c cf 73 8e
+ [112] 7b 07 ce 0c .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr h17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ldr d17, [x5, x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- d4026e495c0bc705 v17.d[0] (xor, xfer vecreg #1)
+ 67c8a1bc8985c705 v17.d[0] (xor, xfer vecreg #1)
095d12c1d2eff385 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr h17, [x5, x6, lsl #1] with x5 = middle_of_block+12, x6=-4
+ldr d17, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 6aa53ab8bb2197e9 v17.d[0] (xor, xfer vecreg #1)
+ 9f6efacc1c85ccbf v17.d[0] (xor, xfer vecreg #1)
b385aca0bf4b9e22 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr h17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ldr d17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 3e6c54815fb41ceb v17.d[0] (xor, xfer vecreg #1)
+ cc0a66b8049d1ceb v17.d[0] (xor, xfer vecreg #1)
7e79af58033aa46b v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr h17, [x5, w6, uxtw #1] with x5 = middle_of_block+12, x6=4
+ldr d17, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 14cc1f374977a711 v17.d[0] (xor, xfer vecreg #1)
+ 40f5582b2ef87247 v17.d[0] (xor, xfer vecreg #1)
ae2dfffc22f127b4 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr h17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ldr d17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- b039006f7f1f742b v17.d[0] (xor, xfer vecreg #1)
+ 3713dafef7c8742b v17.d[0] (xor, xfer vecreg #1)
86947fa19fa34d52 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr h17, [x5, w6, sxtw #1] with x5 = middle_of_block+12, x6=-4
+ldr d17, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- d6275abd045ffef5 v17.d[0] (xor, xfer vecreg #1)
+ c830bee01a533a7f v17.d[0] (xor, xfer vecreg #1)
4ca4145bfe843997 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str b17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+str s17, [x5, x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. 57 .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. 57 21 e8 98 .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str b17, [x5, x6, lsl #0] with x5 = middle_of_block+12, x6=-4
+str s17, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. 90 .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. 0d a5 d4 a1
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str b17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+str s17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 39 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 39 a9 0a ae .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str b17, [x5, w6, uxtw #0] with x5 = middle_of_block+12, x6=4
+str s17, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 56 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. e9 3b 70 4a
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str b17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+str s17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] c4 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] c4 87 1b 47 .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str b17, [x5, w6, sxtw #0] with x5 = middle_of_block+12, x6=-4
+str s17, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. 19 .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. 89 8d 56 12
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr b17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ldr s17, [x5, x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 41d5efcda6de2156 v17.d[0] (xor, xfer vecreg #1)
+ 41d5efcd0e991556 v17.d[0] (xor, xfer vecreg #1)
e9813744a9ef2675 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr b17, [x5, x6, lsl #0] with x5 = middle_of_block+12, x6=-4
+ldr s17, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 451b26983632a3b0 v17.d[0] (xor, xfer vecreg #1)
+ 451b2698d8e0d47e v17.d[0] (xor, xfer vecreg #1)
a5208074ab9d52cc v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr b17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ldr s17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- b7f65aad3a726561 v17.d[0] (xor, xfer vecreg #1)
+ b7f65aadfa88cb61 v17.d[0] (xor, xfer vecreg #1)
b2fce36c334d89c0 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr b17, [x5, w6, uxtw #0] with x5 = middle_of_block+12, x6=4
+ldr s17, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 5bd9f1a0b4530a92 v17.d[0] (xor, xfer vecreg #1)
+ 5bd9f1a0bd7ccf88 v17.d[0] (xor, xfer vecreg #1)
54074141c636eda4 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr b17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ldr s17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- f53a4c05aa893694 v17.d[0] (xor, xfer vecreg #1)
+ f53a4c057ce75594 v17.d[0] (xor, xfer vecreg #1)
cf378107e789a4cc v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr b17, [x5, w6, sxtw #0] with x5 = middle_of_block+12, x6=-4
+ldr s17, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 498cd26f20c78e01 v17.d[0] (xor, xfer vecreg #1)
+ 498cd26f5c579dd3 v17.d[0] (xor, xfer vecreg #1)
667e85d11a7cd18c v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-LDRS{B,H,W} (integer register, SX)
-ldrsw x13, [x5,x6] with x5 = middle_of_block+12, x6=-4
+str h17, [x5, x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. 7f 1c .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 45283e5489578bad x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsw x13, [x5,x6, lsl #2] with x5 = middle_of_block+12, x6=-4
+str h17, [x5, x6, lsl #1] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. 3d 5f .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 38a305c49938b487 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsw x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
+str h17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] a0 7b .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 55d009793f6420d6 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsw x13, [x5,w6,uxtw #2] with x5 = middle_of_block+12, x6=4
+str h17, [x5, w6, uxtw #1] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. 9e d1 .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- b01695c953ae6f8a x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsw x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
+str h17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] ba e6 .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 607cc36833167627 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsw x13, [x5,w6,sxtw #2] with x5 = middle_of_block+12, x6=-4
+str h17, [x5, w6, sxtw #1] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. 33 5d .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 39eb4f850cc79ba6 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsh x13, [x5,x6] with x5 = middle_of_block+12, x6=-4
+ldr h17, [x5, x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 42c23127cfc887a0 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 3733d487937542d5 v17.d[0] (xor, xfer vecreg #1)
+ 0220f16fd2a3c604 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsh x13, [x5,x6, lsl #1] with x5 = middle_of_block+12, x6=-4
+ldr h17, [x5, x6, lsl #1] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 807c4710d2a76a71 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ e95cb7ef93461992 v17.d[0] (xor, xfer vecreg #1)
+ 11772a2f28e2b456 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsh x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
+ldr h17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 49720b298caae7b8 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 3a8b469137744db7 v17.d[0] (xor, xfer vecreg #1)
+ a07a2ba835945b34 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsh x13, [x5,w6,uxtw #1] with x5 = middle_of_block+12, x6=4
+ldr h17, [x5, w6, uxtw #1] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- a7699d0ab48417a3 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ ec32e80181b346fd v17.d[0] (xor, xfer vecreg #1)
+ f41dd9ed7beee1f3 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsh x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
+ldr h17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- e67b59bc63148b29 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ c4c7ffd277b67519 v17.d[0] (xor, xfer vecreg #1)
+ 50541814802369e6 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsh x13, [x5,w6,sxtw #1] with x5 = middle_of_block+12, x6=-4
+ldr h17, [x5, w6, sxtw #1] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 31ad8decd3c3706e x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 86bcef991d31288a v17.d[0] (xor, xfer vecreg #1)
+ fa13cb2fc8681760 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsh w13, [x5,x6] with x5 = middle_of_block+12, x6=-4
+str b17, [x5, x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. 51 .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 8b4666106a2b3d08 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsh w13, [x5,x6, lsl #1] with x5 = middle_of_block+12, x6=-4
+str b17, [x5, x6, lsl #0] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. 91 .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 13d6e5cba693fd33 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsh w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
+str b17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 61 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 2c7554dbfdb54557 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsh w13, [x5,w6,uxtw #1] with x5 = middle_of_block+12, x6=4
+str b17, [x5, w6, uxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] cd .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 999716d25bb7ce2f x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsh w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
+str b17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 0a .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 1db091457728f8cd x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsh w13, [x5,w6,sxtw #1] with x5 = middle_of_block+12, x6=-4
+str b17, [x5, w6, sxtw #0] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. 36 .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 7d3326c8ac434998 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsb x13, [x5,x6] with x5 = middle_of_block+12, x6=-4
+ldr b17, [x5, x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 7d963ceef526ab13 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ b71c207a21cf0a0a v17.d[0] (xor, xfer vecreg #1)
+ 553b42414d0ad433 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsb x13, [x5,x6, lsl #0] with x5 = middle_of_block+12, x6=-4
+ldr b17, [x5, x6, lsl #0] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- e14c354c601b31f6 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 576aedbed15e47bb v17.d[0] (xor, xfer vecreg #1)
+ f68aa9d2371ac2c0 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsb x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
+ldr b17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 6dc87576994ee1f1 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ c62c182d55ba232c v17.d[0] (xor, xfer vecreg #1)
+ 47f48a0b070e1bc8 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsb x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
+ldr b17, [x5, w6, uxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- e4806100a3735e28 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ c6d70459b09642c3 v17.d[0] (xor, xfer vecreg #1)
+ 8d6fc702421a02a2 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsb x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
+ldr b17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0ce65d7d823f4bb6 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 1cdf17d7e6a7491c v17.d[0] (xor, xfer vecreg #1)
+ 0cee45c96b719b9f v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsb x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=-4
+ldr b17, [x5, w6, sxtw #0] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 588f337dc59ab1e9 x13 (xor, xfer intreg #1)
+ 0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 8cb8b23afca0daf8 v17.d[0] (xor, xfer vecreg #1)
+ 0864e77407470a14 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsb w13, [x5,x6] with x5 = middle_of_block+12, x6=-4
+LDRS{B,H,W} (integer register, SX)
+ldrsw x13, [x5,x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 7a9013a2d09a0a55 x13 (xor, xfer intreg #1)
+ 856fec5d1fcac255 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsb w13, [x5,x6, lsl #0] with x5 = middle_of_block+12, x6=-4
+ldrsw x13, [x5,x6, lsl #2] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 49bc9573b76ddc40 x13 (xor, xfer intreg #1)
+ 49bc957329b5f526 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsb w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
+ldrsw x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- d866b8875bffc2ee x13 (xor, xfer intreg #1)
+ d866b887ab2179ee x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsb w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
+ldrsw x13, [x5,w6,uxtw #2] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- ea03dd73156703fa x13 (xor, xfer intreg #1)
+ ea03dd73b1c3ee51 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsb w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
+ldrsw x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 45086acae1f0fbe8 x13 (xor, xfer intreg #1)
+ baf79535c23ad7e8 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldrsb w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=-4
+ldrsw x13, [x5,w6,sxtw #2] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- abe7c322bde705a0 x13 (xor, xfer intreg #1)
+ 54183cdda8472bd1 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-LDR/STR (immediate, SIMD&FP, unsigned offset)
-str q17, [x5, #-32] with x5 = middle_of_block+16, x6=0
+ldrsh x13, [x5,x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 96 01 58 13 1a 26 4d ce 69 8a 7e ae d3 d6 ca f5
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ e1154c0d5c678774 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str d17, [x5, #-32] with x5 = middle_of_block+16, x6=0
+ldrsh x13, [x5,x6, lsl #1] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 8c 9f 74 8b 6b 91 41 e0 .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ 54f897df8f4deee3 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str s17, [x5, #-32] with x5 = middle_of_block+16, x6=0
+ldrsh x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 87 86 06 ee .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ 32d084117f556e17 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr q17, [x5, #-32] with x5 = middle_of_block+16, x6=0
+ldrsh x13, [x5,w6,uxtw #1] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ f4fd14f36dfa6638 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- d3cd22184a47bb9d v17.d[0] (xor, xfer vecreg #1)
- d605cfe1a39c09de v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr d17, [x5, #-32] with x5 = middle_of_block+16, x6=0
+ldrsh x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ 28f4190eaa774c57 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 34b6e1555effb1b9 v17.d[0] (xor, xfer vecreg #1)
- 01020725a8723bf8 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr s17, [x5, #-32] with x5 = middle_of_block+16, x6=0
+ldrsh x13, [x5,w6,sxtw #1] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ 15869377354ce026 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 5c7f1b53537e6e10 v17.d[0] (xor, xfer vecreg #1)
- 8f71d8a1d71aaba8 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-LDR/STR (immediate, SIMD&FP, pre/post index)
-str q17, [x5], #-32 with x5 = middle_of_block+16, x6=0
+ldrsh w13, [x5,x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] ad 0d ad e1 5c 80 83 18 02 ab 2e 69 2a af 3c ea
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ 1306460df86d032d x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str d17, [x5], #-32 with x5 = middle_of_block+16, x6=0
+ldrsh w13, [x5,x6, lsl #1] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 97 67 e8 f0 19 74 5f 91 .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ 680d0b32c7a55d9e x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str s17, [x5], #-32 with x5 = middle_of_block+16, x6=0
+ldrsh w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] f1 c7 64 85 .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ ad03218b72d101ab x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr q17, [x5], #-32 with x5 = middle_of_block+16, x6=0
+ldrsh w13, [x5,w6,uxtw #1] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ a65ce9ab0463a19e x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- eee88871503205b7 v17.d[0] (xor, xfer vecreg #1)
- 9daa3c92e17f7ace v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr d17, [x5], #-32 with x5 = middle_of_block+16, x6=0
+ldrsh w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ 168cca2786589cce x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 7ff4db28862129d8 v17.d[0] (xor, xfer vecreg #1)
- c10b90425585a4b0 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr s17, [x5], #-32 with x5 = middle_of_block+16, x6=0
+ldrsh w13, [x5,w6,sxtw #1] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ c3072693cce83059 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 801fddbc0ac03507 v17.d[0] (xor, xfer vecreg #1)
- f0ed115e260e2db5 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str q17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
+ldrsb x13, [x5,x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 8b 2a 22 e2 f4 e1 22 6a ad fd 45 24 5c 6d 2c 99
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ 6f416183058c33d1 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str d17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
+ldrsb x13, [x5,x6, lsl #0] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 99 dd 1d 76 49 8e 20 85 .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ dfade08a006c63ec x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str s17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
+ldrsb x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] ea 9a cc b5 .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ 283ef8c2d695e2f6 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr q17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
+ldrsb x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ e40fc5cf7cc4fbc5 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- cbf521735120d2b1 v17.d[0] (xor, xfer vecreg #1)
- 9dd4c9c4db2b776b v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr d17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
+ldrsb x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ 91512308ec6d433e x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 1a6feba7bd0f952d v17.d[0] (xor, xfer vecreg #1)
- 2f935e28362648f0 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr s17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
+ldrsb x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ 966f5125dc24e95b x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- f61129e333f8562d v17.d[0] (xor, xfer vecreg #1)
- 8f389fb53ae0f91b v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-LDUR/STUR (unscaled offset, SIMD&FP)
-str q17, [x5, #-13] with x5 = middle_of_block+16, x6=0
+ldrsb w13, [x5,x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. 64 d0 e1 2a ac f5 97 6e 7f f0 36 49 c8
- [144] ff 58 26 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ 55a6fe4fe2a42f1b x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str d17, [x5, #-13] with x5 = middle_of_block+16, x6=0
+ldrsb w13, [x5,x6, lsl #0] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. 2c 05 a1 7b 8e fe b9 a3 .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ 70c94709d638cda0 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-str s17, [x5, #-13] with x5 = middle_of_block+16, x6=0
+ldrsb w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. 44 79 62 32 .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ ab4b8fe649bf686e x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr q17, [x5, #-13] with x5 = middle_of_block+16, x6=0
+ldrsb w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ ca9f3b7b8dc30070 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 2fe82972135e9fb7 v17.d[0] (xor, xfer vecreg #1)
- e8f6cd0891b87a33 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr d17, [x5, #-13] with x5 = middle_of_block+16, x6=0
+ldrsb w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ 913baf5c4ffaece5 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 672f797f523cade3 v17.d[0] (xor, xfer vecreg #1)
- ac79d2b9ac348898 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ldr s17, [x5, #-13] with x5 = middle_of_block+16, x6=0
+ldrsb w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
+ c4924e1d25ba722c x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 1e375ea81ed51e61 v17.d[0] (xor, xfer vecreg #1)
- cd33e286716e72b8 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-LDR (literal, SIMD&FP) (entirely MISSING)
-LD1/ST1 (single structure, no offset)
-st1 {v17.2d}, [x5] with x5 = middle_of_block+3, x6=0
+LDR/STR (immediate, SIMD&FP, unsigned offset)
+str q17, [x5, #-32] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. b1 36 7d 89 19 83 2a 98 fa 1d 4b 25 3a
- [144] b7 ac 8e .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] 1a df ce 86 77 39 e9 ec cc bd 2c 31 d2 61 c0 e4
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.4s}, [x5] with x5 = middle_of_block+5, x6=0
+str d17, [x5, #-32] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. cd 09 39 39 e0 f3 31 35 a1 a8 48
- [144] 1f 3d 55 77 a4 .. .. .. .. .. .. .. .. .. .. ..
+ [112] 3e aa a6 38 d0 29 f0 10 .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.8h}, [x5] with x5 = middle_of_block+7, x6=0
+str s17, [x5, #-32] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. 90 92 d7 4c b6 07 17 77 c2
- [144] ad 50 19 57 84 62 2a .. .. .. .. .. .. .. .. ..
+ [112] e7 3d 73 54 .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.16b}, [x5] with x5 = middle_of_block+13, x6=0
+str h17, [x5, #-32] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. 89 c1 a3
- [144] b6 3a 6e 69 5b ca 06 45 12 47 c8 39 be .. .. ..
+ [112] 05 6b .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.1d}, [x5] with x5 = middle_of_block+3, x6=0
+str b17, [x5, #-32] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. 07 d8 b8 3c e5 d5 40 bd .. .. .. .. ..
+ [112] 88 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.2s}, [x5] with x5 = middle_of_block+5, x6=0
+ldr q17, [x5, #-32] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. 79 0d 09 1f 41 ff 4e f5 .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0119e3ac44783463 v17.d[0] (xor, xfer vecreg #1)
+ 75e709c2a784c7d1 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.4h}, [x5] with x5 = middle_of_block+7, x6=0
+ldr d17, [x5, #-32] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. 12 a3 2c f3 bf e6 48 b9 ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ a5e76f895906b38b v17.d[0] (xor, xfer vecreg #1)
+ cc154357cca832ef v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.8b}, [x5] with x5 = middle_of_block+13, x6=0
+ldr s17, [x5, #-32] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. 79 80 f0
- [144] 75 1c f1 e7 84 .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 5baa73cfd960bf35 v17.d[0] (xor, xfer vecreg #1)
+ 249f48da74ee9d60 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.2d}, [x5] with x5 = middle_of_block+3, x6=0
+ldr h17, [x5, #-32] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- f2660509f772e2c4 v17.d[0] (xor, xfer vecreg #1)
- 5b467ae7606de21d v17.d[1] (xor, xfer vecreg #1)
+ ebc9b52256317cc0 v17.d[0] (xor, xfer vecreg #1)
+ 554c2e4eaba05917 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.4s}, [x5] with x5 = middle_of_block+5, x6=0
+ldr b17, [x5, #-32] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 26785b25bc1f523a v17.d[0] (xor, xfer vecreg #1)
- ec0beb6d405fb626 v17.d[1] (xor, xfer vecreg #1)
+ 35d9207a220d7c4b v17.d[0] (xor, xfer vecreg #1)
+ a211d8c7f4f18c65 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.8h}, [x5] with x5 = middle_of_block+7, x6=0
+LDR/STR (immediate, SIMD&FP, pre/post index)
+str q17, [x5], #-32 with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] cf 57 90 a4 95 88 04 92 cf 79 2f 93 5b fa 98 18
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- a182132e7098bfdb v17.d[0] (xor, xfer vecreg #1)
- 00422b4ce12a3b2e v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.16b}, [x5] with x5 = middle_of_block+13, x6=0
+str d17, [x5], #-32 with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 6a 75 ca 05 7f fd 9d d9 .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0dd07cb167a99f13 v17.d[0] (xor, xfer vecreg #1)
- d97cb1169d9edc1b v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.1d}, [x5] with x5 = middle_of_block+3, x6=0
+str s17, [x5], #-32 with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] b6 5a 86 ac .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 15647e9ff5b3386a v17.d[0] (xor, xfer vecreg #1)
- e079591466a95129 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.2s}, [x5] with x5 = middle_of_block+5, x6=0
+str h17, [x5], #-32 with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] a2 d4 .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 32be7bd672ef1712 v17.d[0] (xor, xfer vecreg #1)
- 4926fd682180c520 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.4h}, [x5] with x5 = middle_of_block+7, x6=0
+str b17, [x5], #-32 with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 20 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 95c62b0621fcf89b v17.d[0] (xor, xfer vecreg #1)
- 22afda2482fa6253 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.8b}, [x5] with x5 = middle_of_block+13, x6=0
+ldr q17, [x5], #-32 with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- e27a083b196210e4 v17.d[0] (xor, xfer vecreg #1)
- b109d45d0d4c4d17 v17.d[1] (xor, xfer vecreg #1)
+ 8e647c8819a0cb22 v17.d[0] (xor, xfer vecreg #1)
+ 5194134631ba2bdf v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-LD1/ST1 (single structure, post index)
-st1 {v17.2d}, [x5], #16 with x5 = middle_of_block+3, x6=0
+ldr d17, [x5], #-32 with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. 77 15 28 7c 59 c4 e2 f4 8d 36 8e 8c db
- [144] e7 10 16 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ f92312f3d743799c v17.d[0] (xor, xfer vecreg #1)
+ 3826ce2647aaabbf v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.4s}, [x5], #16 with x5 = middle_of_block+5, x6=0
+ldr s17, [x5], #-32 with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. f8 dc 82 a1 fa 03 d0 27 6b 33 e2
- [144] 41 9a a2 0b 54 .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 8599356a43337b6c v17.d[0] (xor, xfer vecreg #1)
+ fdfbad94b3469f9f v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.8h}, [x5], #16 with x5 = middle_of_block+7, x6=0
+ldr h17, [x5], #-32 with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. 59 3c b9 a4 36 8b 0b db e3
- [144] 54 63 78 62 da 3c 68 .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ cb86abfa3e48f085 v17.d[0] (xor, xfer vecreg #1)
+ 427c54bbd5574c0b v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.16b}, [x5], #16 with x5 = middle_of_block+13, x6=0
+ldr b17, [x5], #-32 with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. 5f 9f 80
- [144] 9f f8 7b 27 0f 13 e1 67 98 5d 96 1f 53 .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 74eb3258df25d2dd v17.d[0] (xor, xfer vecreg #1)
+ 4c9da8af320ed858 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.1d}, [x5], #8 with x5 = middle_of_block+3, x6=0
+str q17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. 6c 47 e2 9f 85 67 39 4a .. .. .. .. ..
+ [112] 25 bc 55 91 06 10 32 52 c7 ac c2 3c 47 90 5e 43
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.2s}, [x5], #8 with x5 = middle_of_block+5, x6=0
+str d17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. f4 61 02 67 69 4f 5d 87 .. .. ..
+ [112] c5 ab f4 72 0f 18 f3 d9 .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.4h}, [x5], #8 with x5 = middle_of_block+7, x6=0
+str s17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. 5b 3c 6e 1b 7e 1b 5d ad ..
+ [112] ac a5 47 fc .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.8b}, [x5], #8 with x5 = middle_of_block+13, x6=0
+str h17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. 60 9f 3d
- [144] fd aa ff d4 98 .. .. .. .. .. .. .. .. .. .. ..
+ [112] c6 78 .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.2d}, [x5], #16 with x5 = middle_of_block+3, x6=0
+str b17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] 05 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 742ee30b26c3644a v17.d[0] (xor, xfer vecreg #1)
- a15d19c498909d48 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.4s}, [x5], #16 with x5 = middle_of_block+5, x6=0
+ldr q17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 17472b2eddb28e7d v17.d[0] (xor, xfer vecreg #1)
- a4bd787fae4b47c8 v17.d[1] (xor, xfer vecreg #1)
+ 6e66596f446314a9 v17.d[0] (xor, xfer vecreg #1)
+ 0cb796190afeb988 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.8h}, [x5], #16 with x5 = middle_of_block+7, x6=0
+ldr d17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- e44eda3a8b4e1b86 v17.d[0] (xor, xfer vecreg #1)
- a1ff95d9a002913d v17.d[1] (xor, xfer vecreg #1)
+ 3e37d197117befb1 v17.d[0] (xor, xfer vecreg #1)
+ 6913a44d6c76c585 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.16b}, [x5], #16 with x5 = middle_of_block+13, x6=0
+ldr s17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 883e8f331f6b3363 v17.d[0] (xor, xfer vecreg #1)
- 725a87635ce35250 v17.d[1] (xor, xfer vecreg #1)
+ 5879c692e0f48806 v17.d[0] (xor, xfer vecreg #1)
+ 2a846d762bba52a3 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.1d}, [x5], #8 with x5 = middle_of_block+3, x6=0
+ldr h17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 599b273df848aa3e v17.d[0] (xor, xfer vecreg #1)
+ e483802e85cfdd51 v17.d[0] (xor, xfer vecreg #1)
1328e620c9790196 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.2s}, [x5], #8 with x5 = middle_of_block+5, x6=0
+ldr b17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 409538166d7f5536 v17.d[0] (xor, xfer vecreg #1)
+ 7b8e33618bfcad4a v17.d[0] (xor, xfer vecreg #1)
6af5f45fc9e7f5b0 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
+ -32 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.4h}, [x5], #8 with x5 = middle_of_block+7, x6=0
+LDUR/STUR (unscaled offset, SIMD&FP)
+str q17, [x5, #-13] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. c9 09 c1 88 13 fc 06 6c b4 ae ed ae 8b
+ [144] 5f ca 40 .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- be28464529e28fc0 v17.d[0] (xor, xfer vecreg #1)
- 71de7b47b0395447 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1 {v17.8b}, [x5], #8 with x5 = middle_of_block+13, x6=0
+str d17, [x5, #-13] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. 1b 3f c9 e8 fb e2 6c 8d .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 5efd0ad9d00cf616 v17.d[0] (xor, xfer vecreg #1)
- 6dd65eeb01a241ae v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-LD1R (single structure, replicate)
-ld1r {v17.2d}, [x5] with x5 = middle_of_block+3, x6=-5
+str s17, [x5, #-13] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. bd 34 d2 2f .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 16e55b1873ee34c3 v17.d[0] (xor, xfer vecreg #1)
- 960bd53c91a65576 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.1d}, [x5] with x5 = middle_of_block+3, x6=-4
+str h17, [x5, #-13] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. 6c 47 .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 2d3307d50522c7ac v17.d[0] (xor, xfer vecreg #1)
- 54c8cabaf18c553d v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.4s}, [x5] with x5 = middle_of_block+3, x6=-3
+str b17, [x5, #-13] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. ea .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 8565377c153c682e v17.d[0] (xor, xfer vecreg #1)
- 8f7d2d10d0a6f211 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.2s}, [x5] with x5 = middle_of_block+3, x6=-2
+ldr q17, [x5, #-13] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 852c4163a404b939 v17.d[0] (xor, xfer vecreg #1)
- 3e69586bbb4352fd v17.d[1] (xor, xfer vecreg #1)
+ 43662152a404b939 v17.d[0] (xor, xfer vecreg #1)
+ 7459c2e00c9a57da v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.8h}, [x5] with x5 = middle_of_block+3, x6=-1
+ldr d17, [x5, #-13] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 82ec485fcb1df671 v17.d[0] (xor, xfer vecreg #1)
- 81161900a3c65e8a v17.d[1] (xor, xfer vecreg #1)
+ 683f58edc2f5f671 v17.d[0] (xor, xfer vecreg #1)
+ fefd66ebdc2d2161 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.4h}, [x5] with x5 = middle_of_block+3, x6=1
+ldr s17, [x5, #-13] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 450ff000f252c2cc v17.d[0] (xor, xfer vecreg #1)
+ 726ac7656f6fc2cc v17.d[0] (xor, xfer vecreg #1)
4b5928a07f68578d v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.16b}, [x5] with x5 = middle_of_block+3, x6=2
+ldr h17, [x5, #-13] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 8cb88f8590be7a3c v17.d[0] (xor, xfer vecreg #1)
- 3328dec7727f4c8c v17.d[1] (xor, xfer vecreg #1)
+ d6e2d5dfcae48c3c v17.d[0] (xor, xfer vecreg #1)
+ 6972849d282516d6 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.8b}, [x5] with x5 = middle_of_block+3, x6=3
+ldr b17, [x5, #-13] with x5 = middle_of_block+16, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- b5bd9ae99becf0fa v17.d[0] (xor, xfer vecreg #1)
+ ebe3c4b7c5b2aefa v17.d[0] (xor, xfer vecreg #1)
9c3a5cf75b9a848f v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.2d}, [x5], #8 with x5 = middle_of_block+3, x6=-5
+LDR (literal, SIMD&FP) (entirely MISSING)
+xyzzy10: ldr s17, xyzzy10 - 8 with x5 = middle_of_block+0, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- a9d70e88d1e89d30 v17.d[0] (xor, xfer vecreg #1)
- f79063caf0461a0b v17.d[1] (xor, xfer vecreg #1)
+ 76e0f98045156b32 v17.d[0] (xor, xfer vecreg #1)
+ 28a794c29dfbc40c v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.1d}, [x5], #8 with x5 = middle_of_block+3, x6=-4
+xyzzy11: ldr d17, xyzzy11 + 8 with x5 = middle_of_block+0, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 6e29d7586e832013 v17.d[0] (xor, xfer vecreg #1)
+ 07cfd3de4a8087e3 v17.d[0] (xor, xfer vecreg #1)
50ab1111717bfaa1 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.4s}, [x5], #4 with x5 = middle_of_block+3, x6=-3
+xyzzy12: ldr q17, xyzzy12 + 4 with x5 = middle_of_block+0, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 8a2bf5aadb6f253e v17.d[0] (xor, xfer vecreg #1)
- 2db380692bc77c30 v17.d[1] (xor, xfer vecreg #1)
+ 04a3c72e55e713a0 v17.d[0] (xor, xfer vecreg #1)
+ 67bbbee861cf4eb2 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 4 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.2s}, [x5], #4 with x5 = middle_of_block+3, x6=-2
+LD1/ST1 (multiple 1-elem structs to/from 1 reg
+st1 {v18.2d}, [x5] with x5 = middle_of_block+17, x6=7
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 75 b4 f8 ea 41 a0 6a 0e 6e 63 47 f2 e4 c5 6f
+ [160] 45 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 5f4fbbd1703f0fa6 v17.d[0] (xor, xfer vecreg #1)
- 884b698ee1aad864 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 4 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.8h}, [x5], #2 with x5 = middle_of_block+3, x6=-1
+st1 {v18.2d}, [x5], #16 with x5 = middle_of_block+9, x6=9
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 23 6a 6f 3d e8 28 2c
+ [144] ca 2b aa fa 5c 33 13 28 bd .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 5f54873569a67df4 v17.d[0] (xor, xfer vecreg #1)
- cc4dd879575d1ba7 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 2 x5 (sub, base reg)
+ 16 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.4h}, [x5], #2 with x5 = middle_of_block+3, x6=1
+st1 {v18.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. ab fa ea e8 e7 3d bb 50 27 18 9c c2 33
+ [128] c3 dc a1 .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 06a027f230b4e536 v17.d[0] (xor, xfer vecreg #1)
- 63bc830ecac63e78 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 2 x5 (sub, base reg)
+ -5 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.16b}, [x5], #1 with x5 = middle_of_block+3, x6=2
+st1 {v18.1d}, [x5] with x5 = middle_of_block+17, x6=7
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 8f 11 dc 1c fd cb 48 71 .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 85340ca9c236f0cf v17.d[0] (xor, xfer vecreg #1)
- 5fc374e5f13799b4 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 1 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.8b}, [x5], #1 with x5 = middle_of_block+3, x6=3
+st1 {v18.1d}, [x5], #8 with x5 = middle_of_block+9, x6=9
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 50 34 d5 19 76 a2 df
+ [144] 47 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 6c96cd195109f73a v17.d[0] (xor, xfer vecreg #1)
- 019c7f314c704d7d v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 1 x5 (sub, base reg)
+ 8 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.2d}, [x5], x6 with x5 = middle_of_block+3, x6=-5
+st1 {v18.1d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 54 af 11 73 80 73 52 91 .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 10d519a8e28f969d v17.d[0] (xor, xfer vecreg #1)
- cb6c9dd1de5b705c v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
-5 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.1d}, [x5], x6 with x5 = middle_of_block+3, x6=-4
+st1 {v18.4s}, [x5] with x5 = middle_of_block+17, x6=7
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 52 0a f9 e8 d3 0f d4 4a 90 c2 aa 6c 9d 64 9e
+ [160] 55 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- ca6b9bc3d677891a v17.d[0] (xor, xfer vecreg #1)
- 838c7e9788492413 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -4 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.4s}, [x5], x6 with x5 = middle_of_block+3, x6=-3
+st1 {v18.4s}, [x5], #16 with x5 = middle_of_block+9, x6=9
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. c6 c8 bc 43 4f af 99
+ [144] c1 1e 81 c6 52 11 e0 fe e1 .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 4e0a668838db0780 v17.d[0] (xor, xfer vecreg #1)
- c915f2e25fd1deb1 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -3 x5 (sub, base reg)
+ 16 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.2s}, [x5], x6 with x5 = middle_of_block+3, x6=-2
+st1 {v18.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 03 18 4d 54 bd 94 7c 21 6d 3e dc cd 8f
+ [128] c6 7e 13 .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0ea3ee03571abe8c v17.d[0] (xor, xfer vecreg #1)
- 082ca0e09defe4da v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -2 x5 (sub, base reg)
+ -5 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.8h}, [x5], x6 with x5 = middle_of_block+3, x6=-1
+st1 {v18.2s}, [x5] with x5 = middle_of_block+17, x6=7
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 9b df ef 4d 25 29 2c 18 .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- ecf4aa34e8a3e4bb v17.d[0] (xor, xfer vecreg #1)
- 0b9daa36be0c891f v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -1 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.4h}, [x5], x6 with x5 = middle_of_block+3, x6=1
+st1 {v18.2s}, [x5], #8 with x5 = middle_of_block+9, x6=9
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. e6 e5 46 3d 53 91 f8
+ [144] 32 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 2809ca6757d53c1b v17.d[0] (xor, xfer vecreg #1)
- b01c03abab03ab72 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 1 x5 (sub, base reg)
+ 8 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.16b}, [x5], x6 with x5 = middle_of_block+3, x6=2
+st1 {v18.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. f8 55 a0 6f 60 40 bb 60 .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 07610b48353830da v17.d[0] (xor, xfer vecreg #1)
- dfb72bf7f9bb0e3d v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 2 x5 (sub, base reg)
+ -5 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld1r {v17.8b}, [x5], x6 with x5 = middle_of_block+3, x6=3
+st1 {v18.8h}, [x5] with x5 = middle_of_block+17, x6=7
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 4d d1 5e 4d 51 dc 70 5a b2 d4 11 4e a3 21 1e
+ [160] b7 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- b4b0927d64523028 v17.d[0] (xor, xfer vecreg #1)
- 9cfcc99ad3259c7a v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 3 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-LD2/ST2 (multiple 2-elem structs to/from 2/regs, post index) (VERY INCOMPLETE)
-ld2 {v17.2d, v18.2d}, [x5], #32 with x5 = middle_of_block+3, x6=0
+st1 {v18.8h}, [x5], #16 with x5 = middle_of_block+9, x6=9
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 0d 4c 92 85 65 87 9c
+ [144] 9f 13 3d 3b 04 7e 3e 0a ed .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 598fa18805362a36 v17.d[0] (xor, xfer vecreg #1)
- a049325334115b15 v17.d[1] (xor, xfer vecreg #1)
- 67c0486234ea31a8 v18.d[0] (xor, xfer vecreg #2)
- 543b8c6a719a028a v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
+ 16 x5 (sub, base reg)
0 x6 (sub, index reg)
-st2 {v17.2d, v18.2d}, [x5], #32 with x5 = middle_of_block+7, x6=0
+st1 {v18.8h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. 4c ca 71 25 f5 5d 71 24 ec
- [144] 1f 20 ab dd e6 df a3 ad 4d 6d 1c 9d 7b 57 62 76
- [160] 0d 49 0f e2 1c 9c 09 .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 74 86 09 a1 28 18 90 ac 0f d4 72 97 41
+ [128] 95 f5 a1 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
+ -5 x5 (sub, base reg)
0 x6 (sub, index reg)
-ld2 {v17.4s, v18.4s}, [x5], #32 with x5 = middle_of_block+13, x6=0
+st1 {v18.4h}, [x5] with x5 = middle_of_block+17, x6=7
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 46 20 e7 e6 b8 e6 c0 91 .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- d8ca83d90f51a16e v17.d[0] (xor, xfer vecreg #1)
- 685f5274289bf458 v17.d[1] (xor, xfer vecreg #1)
- 7544fd2f2a6b60ba v18.d[0] (xor, xfer vecreg #2)
- b821f98608fbfdb7 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
+ 0 x5 (sub, base reg)
0 x6 (sub, index reg)
-st2 {v17.4s, v18.4s}, [x5], #32 with x5 = middle_of_block+17, x6=0
+st1 {v18.4h}, [x5], #8 with x5 = middle_of_block+9, x6=9
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. 85 12 2b fe 66 67 4e 3c 64 02 15 94 d9 2a fb
- [160] f2 02 b5 4a 55 d9 22 03 ce 49 fd 5f cf 7f ea a7
- [176] c1 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 9e bb c1 9e 60 d2 25
+ [144] 06 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
+ 8 x5 (sub, base reg)
0 x6 (sub, index reg)
-LD1/ST1 (multiple 1-elem structs to/from 2 regs, no offset) (VERY INCOMPLETE)
-ld1 {v17.16b, v18.16b}, [x5] with x5 = middle_of_block+3, x6=0
+st1 {v18.4h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. b6 cc 88 cb d7 ba 7b 69 .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- f48bca244233353a v17.d[0] (xor, xfer vecreg #1)
- 05148f737096f9a8 v17.d[1] (xor, xfer vecreg #1)
- 0d466b7dee654778 v18.d[0] (xor, xfer vecreg #2)
- d120529f0466f486 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
+ -5 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.16b, v18.16b}, [x5] with x5 = middle_of_block+7, x6=0
+st1 {v18.16b}, [x5] with x5 = middle_of_block+17, x6=7
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. 46 f3 cf e8 18 19 cf 46 5b
- [144] 0f 99 05 8d a4 82 74 34 35 26 a7 7e b9 cf b1 f1
- [160] 0c 3c 20 10 ed b7 38 .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 68 0b 28 19 ba 06 3c 3f d2 98 7e 98 f3 fb ed
+ [160] 6e .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-LD1/ST1 (multiple 1-elem structs to/from 2 regs, post index) (VERY INCOMPLETE)
-ld1 {v17.16b, v18.16b}, [x5], #32 with x5 = middle_of_block+3, x6=0
+st1 {v18.16b}, [x5], #16 with x5 = middle_of_block+9, x6=9
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. f7 f5 f1 04 28 b1 33
+ [144] 65 0b df 59 72 7b 2f 4a e0 .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 48d6b35f479f9d54 v17.d[0] (xor, xfer vecreg #1)
- e557b017f60e9044 v17.d[1] (xor, xfer vecreg #1)
- f4c584a1e96d4812 v18.d[0] (xor, xfer vecreg #2)
- 661edc799d4c18b9 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
+ 16 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.16b, v18.16b}, [x5], #32 with x5 = middle_of_block+7, x6=0
+st1 {v18.16b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. 2f 6e 27 85 51 e7 22 9c 4f
- [144] 29 76 62 56 8d d1 c6 93 43 13 02 89 e0 f3 0a 1c
- [160] e2 bf 34 0c f6 88 24 .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. 45 1d cc 2a c8 f9 f3 0a dc 60 20 4a
+ [128] 31 40 4a .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
+ -5 x5 (sub, base reg)
0 x6 (sub, index reg)
-LD1/ST1 (multiple 1-elem structs to/from 3 regs, no offset) (VERY INCOMPLETE)
-ld1 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+3, x6=0
+st1 {v18.8b}, [x5] with x5 = middle_of_block+17, x6=7
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 90 d2 c3 e8 b6 .. 05 e0 .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- f7753828f47873cf v17.d[0] (xor, xfer vecreg #1)
- db451740446b05f7 v17.d[1] (xor, xfer vecreg #1)
- d18aaa1960c21613 v18.d[0] (xor, xfer vecreg #2)
- 20887bf91e32066e v18.d[1] (xor, xfer vecreg #2)
- e1bdab4f96ef5135 v19.d[0] (xor, xfer vecreg #3)
- 085e0725b9e776b2 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+7, x6=0
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v18.8b}, [x5], #8 with x5 = middle_of_block+9, x6=9
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. 60 d8 45 a0 4c 01 36 cc 8c
- [144] 13 db dd 64 21 23 11 3a .. 46 1a 58 12 59 7d 8e
- [160] 47 49 a4 4c 6a db 4a 2c fe 05 1b a2 ed c9 c7 38
- [176] af .. 6c fb 93 65 4e .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 79 b8 44 3a 9c 66 67
+ [144] c0 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v18.8b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 90 14 c7 85 e2 e1 8e ae .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.2d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0e49900e4fabdee1 v18.d[0] (xor, xfer vecreg #2)
+ 980f0cb2ca770e1e v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-LD3/ST3 (multiple 3-elem structs to/from 3/regs, post index) (VERY INCOMPLETE)
-ld3 {v17.2d, v18.2d, v19.2d}, [x5], #48 with x5 = middle_of_block+13, x6=0
+ld1 {v18.2d}, [x5], #16 with x5 = middle_of_block+9, x6=9
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 9fb44ce1636e0b23 v17.d[0] (xor, xfer vecreg #1)
- 0bcd85ee81174863 v17.d[1] (xor, xfer vecreg #1)
- 50619b14a34f9626 v18.d[0] (xor, xfer vecreg #2)
- 4c7b15f65ab9658e v18.d[1] (xor, xfer vecreg #2)
- de008e511a9a7f25 v19.d[0] (xor, xfer vecreg #3)
- cd74fadb99277653 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 34a0feac46f9c584 v18.d[0] (xor, xfer vecreg #2)
+ bb40d10aa460ab0e v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 48 x5 (sub, base reg)
+ 16 x5 (sub, base reg)
0 x6 (sub, index reg)
-st3 {v17.2d, v18.2d, v19.2d}, [x5], #48 with x5 = middle_of_block+17, x6=0
+ld1 {v18.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. 4d fd 5a dd 39 59 7f 4d f1 ea d1 2e d9 a4 57
- [160] a0 c7 62 e7 bc cd af ce 50 c8 3d 08 ea 35 88 31
- [176] cb ac f8 86 1e e0 77 a4 a4 01 74 07 44 09 b0 e9
- [192] a9 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 365ea647ea88f6e5 v18.d[0] (xor, xfer vecreg #2)
+ 15a1ae6f99a97ca2 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 48 x5 (sub, base reg)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.1d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 06078920d19c0f89 v18.d[0] (xor, xfer vecreg #2)
+ 7f2b0d18312277d4 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.1d}, [x5], #8 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 62424b0ff6d05a98 v18.d[0] (xor, xfer vecreg #2)
+ 33b5d2c7b684bc1f v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.1d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ ee74ca85e1615385 v18.d[0] (xor, xfer vecreg #2)
+ a652cd051020092c v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.4s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 9de88bf514ee5f19 v18.d[0] (xor, xfer vecreg #2)
+ ef820dbfe7b93530 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.4s}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ abe21c41cfd6495c v18.d[0] (xor, xfer vecreg #2)
+ 816a46e081b16a3f v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 57c9b01240dc49ad v18.d[0] (xor, xfer vecreg #2)
+ 2c7750e593ce4f1d v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.2s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 08a24d1427d79701 v18.d[0] (xor, xfer vecreg #2)
+ 3687ac1f11de5e88 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.2s}, [x5], #8 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 15ef82a359fa23e7 v18.d[0] (xor, xfer vecreg #2)
+ 60c915534ca5ef4c v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 7851cade28fe17b0 v18.d[0] (xor, xfer vecreg #2)
+ e0d50c8d73de61cb v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.8h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 1dd94589132cbeff v18.d[0] (xor, xfer vecreg #2)
+ 7e7bc165f92233dd v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.8h}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 7af92cf06b44f59b v18.d[0] (xor, xfer vecreg #2)
+ eb7f97552c69ea0a v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.8h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ d76c28b287a76a47 v18.d[0] (xor, xfer vecreg #2)
+ e76a33be4d4ca8ef v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.4h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ ce0b83d4fdf6bd68 v18.d[0] (xor, xfer vecreg #2)
+ 94f949499d3fb79c v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.4h}, [x5], #8 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 636c1bed8f0d9165 v18.d[0] (xor, xfer vecreg #2)
+ c24365d11ebba5aa v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.4h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ dedd9db410fa32d5 v18.d[0] (xor, xfer vecreg #2)
+ df0f67d7a3e14b6a v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ f96b5ff5e25e7c1f v18.d[0] (xor, xfer vecreg #2)
+ effaf2e233a5a64a v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.16b}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ f0bdf210ab472b0c v18.d[0] (xor, xfer vecreg #2)
+ 43a7e502819ce40a v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.16b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 666c4c35d6dbee73 v18.d[0] (xor, xfer vecreg #2)
+ 09badcda468fad86 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.8b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ ef021323042b101f v18.d[0] (xor, xfer vecreg #2)
+ f86243743525e5f0 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.8b}, [x5], #8 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ df466fa2055ceac5 v18.d[0] (xor, xfer vecreg #2)
+ bb0422208ca63f17 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v18.8b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0e207f30dacabe39 v18.d[0] (xor, xfer vecreg #2)
+ 05e040c300082ae8 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LD2/ST2 (multiple 2-elem structs to/from 2 regs
+st2 {v18.2d, v19.2d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. bc d8 05 33 8b 60 19 1f 40 16 34 68 5e d0 ec
+ [160] 6d 27 b7 ae c3 bf 0f b2 cc b8 01 8b f7 87 44 ba
+ [176] 9d .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.2d, v19.2d}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 15 7e d4 .. 40 52 e5
+ [144] df 71 58 19 72 48 06 55 43 52 65 32 3e 8c c3 9e
+ [160] d8 0c b5 bc 5c 2e 4f fc a8 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.2d, v19.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 41 c2 a7 b5 fa de f1 4c 8b 9d 33 b4 65
+ [128] e3 8d 38 87 5c 81 01 49 47 e6 60 b6 be e4 64 2c
+ [144] ec 0c 60 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.4s, v19.4s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 52 fd 7c 05 bd fc 94 9f 73 3c 4d aa 4d fa fd
+ [160] 4a 59 5d 3d 04 1d e9 99 65 0f 26 c3 b8 d9 5b ed
+ [176] d5 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.4s, v19.4s}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. cf e1 5c cb 12 a4 a1
+ [144] 33 d0 4a 42 94 53 d7 38 e0 05 81 7d cc 18 b1 bc
+ [160] 33 44 20 28 5f 82 ad 73 9a .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.4s, v19.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 52 bb 2d bb b0 56 20 2f 2c e2 f2 25 84
+ [128] d3 9a a9 05 0d 60 6f b3 a2 a3 d5 14 26 73 b6 c2
+ [144] 19 8d cd .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.2s, v19.2s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 91 bd 2c 71 b8 74 64 03 d2 86 f1 0b 56 18 04
+ [160] a1 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.2s, v19.2s}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. d1 0b 68 e7 da 2f 9e
+ [144] 05 9e cc 4b 98 4a 39 0a 9c .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.2s, v19.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 68 68 ca 1a 74 1a 3a 21 b4 ff 40 19 e3
+ [128] 43 de e4 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.8h, v19.8h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 56 5b 18 58 be 0f 0f 95 77 4e a4 44 8f 6a 9f
+ [160] 72 79 e7 d9 ea 13 3e ef f9 61 a3 20 35 d3 23 01
+ [176] c2 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.8h, v19.8h}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 7c c0 2a 44 6d 07 0f
+ [144] c9 b4 d9 07 37 c8 bc ea f5 c9 3c 4f 03 c1 53 ea
+ [160] 5d b2 08 f9 75 84 02 b9 ac .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.8h, v19.8h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. c6 e9 15 06 79 c1 f8 7c d8 49 66 43 c1
+ [128] 08 57 cd c9 23 a3 1e 83 38 73 1d 9a 2a 65 8a 9d
+ [144] bc 70 cc .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.4h, v19.4h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 84 14 86 fb c8 8b f3 15 82 13 37 3f e9 84 70
+ [160] be .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.4h, v19.4h}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 30 bf 19 8c 93 86 d4
+ [144] c0 b1 6f 28 5d d9 f6 f8 6f .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.4h, v19.4h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. ab 5f 10 ed bb 9c 18 dc 19 20 7e b9 84
+ [128] 4e 06 40 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.16b, v19.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. f9 f2 61 b9 64 78 86 42 14 63 a9 8d 17 ff 6d
+ [160] 83 14 86 ff c3 d9 f4 08 ef e8 4d 6c dd c7 60 69
+ [176] 05 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.16b, v19.16b}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 4c c3 e9 82 dc da d8
+ [144] 29 35 09 45 ca 30 a2 58 87 8d ed f6 cf ac 99 1e
+ [160] fe 59 7c .. be f5 43 7e a6 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.16b, v19.16b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 56 04 e0 0c f9 7a 12 e5 f8 b6 c2 18 9f
+ [128] 0b 98 1f 41 4d f0 7e e3 02 9e ee ef 7e f2 d7 80
+ [144] fe 78 26 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.8b, v19.8b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 96 d6 47 b0 92 33 a9 dc 4b 80 b4 8e 5a fe 35
+ [160] c3 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.8b, v19.8b}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 32 f9 ee c7 c9 b4 aa
+ [144] 44 e1 cb 37 5f 8c b3 d6 be .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.8b, v19.8b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 06 ca 56 63 95 90 2d 35 f4 87 f8 a0 b2
+ [128] ce 7e 4b .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.2d, v19.2d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 631009fa91e5bfc5 v18.d[0] (xor, xfer vecreg #2)
+ 1baf3da670ac0a56 v18.d[1] (xor, xfer vecreg #2)
+ 8c66ce590571b73f v19.d[0] (xor, xfer vecreg #3)
+ 6e5baf8b3c66bf59 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.2d, v19.2d}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 4d978be88fe41cc3 v18.d[0] (xor, xfer vecreg #2)
+ a4c6f7100676d9d1 v18.d[1] (xor, xfer vecreg #2)
+ 758b34262ec0228a v19.d[0] (xor, xfer vecreg #3)
+ 992442f5ccf2ae68 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.2d, v19.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ e13595e2b6644802 v18.d[0] (xor, xfer vecreg #2)
+ 9314298cf00feeb1 v18.d[1] (xor, xfer vecreg #2)
+ a2d6756680ee0860 v19.d[0] (xor, xfer vecreg #3)
+ 25d12d1e237e6a91 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.4s, v19.4s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ bf0e162eef0e6948 v18.d[0] (xor, xfer vecreg #2)
+ d857f40e374c7b7d v18.d[1] (xor, xfer vecreg #2)
+ 535864d7aab59b97 v19.d[0] (xor, xfer vecreg #3)
+ dfd451e6e8a6089d v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.4s, v19.4s}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 4c1e535203a7b83e v18.d[0] (xor, xfer vecreg #2)
+ f1449bd19ba96423 v18.d[1] (xor, xfer vecreg #2)
+ 9680b8836ddb4928 v19.d[0] (xor, xfer vecreg #3)
+ 9198c190f49ca9cf v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.4s, v19.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ b0e3894384dcc684 v18.d[0] (xor, xfer vecreg #2)
+ 16c1c9768603a8f3 v18.d[1] (xor, xfer vecreg #2)
+ 042e9a492a80e8ca v19.d[0] (xor, xfer vecreg #3)
+ 49eff04a5f92c4b4 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.2s, v19.2s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 5eddc16846dce323 v18.d[0] (xor, xfer vecreg #2)
+ 6c88bd08080c49f2 v18.d[1] (xor, xfer vecreg #2)
+ 5d83aa5cbf022b85 v19.d[0] (xor, xfer vecreg #3)
+ fc8a95dea2de3051 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.2s, v19.2s}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 90949771458fcab5 v18.d[0] (xor, xfer vecreg #2)
+ 88915e9afe55b2c8 v18.d[1] (xor, xfer vecreg #2)
+ 216d7bb249df7fac v19.d[0] (xor, xfer vecreg #3)
+ f85bb13a277ade8f v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.2s, v19.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ eee870ac4884e95f v18.d[0] (xor, xfer vecreg #2)
+ 246bf67a8897e420 v18.d[1] (xor, xfer vecreg #2)
+ afede95530de958e v19.d[0] (xor, xfer vecreg #3)
+ d96b9a04065d8b4d v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.8h, v19.8h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ a1507328e506c928 v18.d[0] (xor, xfer vecreg #2)
+ 10d1b20d64249f81 v18.d[1] (xor, xfer vecreg #2)
+ 8455f5b29d25abfe v19.d[0] (xor, xfer vecreg #3)
+ 781a9cda02c96a32 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.8h, v19.8h}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 31d4497811d9fd6e v18.d[0] (xor, xfer vecreg #2)
+ 0e93842c42f39ac0 v18.d[1] (xor, xfer vecreg #2)
+ 76e9419ab45e8d1e v19.d[0] (xor, xfer vecreg #3)
+ 7c99d1d4d228e8b1 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.8h, v19.8h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 1e7f4d033fe2680c v18.d[0] (xor, xfer vecreg #2)
+ bf554b127ea88416 v18.d[1] (xor, xfer vecreg #2)
+ 95b2b2eac308efe2 v19.d[0] (xor, xfer vecreg #3)
+ 24f7e58c41bf8805 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.4h, v19.4h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ a49f5c806e3e78a4 v18.d[0] (xor, xfer vecreg #2)
+ d61ac79fcb6f4a26 v18.d[1] (xor, xfer vecreg #2)
+ fc87ff32bcdc7049 v19.d[0] (xor, xfer vecreg #3)
+ 9c3e0af95bc6fad8 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.4h, v19.4h}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ a0fba4f96abe4190 v18.d[0] (xor, xfer vecreg #2)
+ e75b8c35f69c80f5 v18.d[1] (xor, xfer vecreg #2)
+ 24f544470c23ab5d v19.d[0] (xor, xfer vecreg #3)
+ f1db4e0eba1bb903 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.4h, v19.4h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ d8b62f30d73c4b7e v18.d[0] (xor, xfer vecreg #2)
+ 10269f91cefc563e v18.d[1] (xor, xfer vecreg #2)
+ cebfacecf126ae52 v19.d[0] (xor, xfer vecreg #3)
+ c36fb6078cef4ea7 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.16b, v19.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 756a30453ee3ebb9 v18.d[0] (xor, xfer vecreg #2)
+ 392a7695a1f15215 v18.d[1] (xor, xfer vecreg #2)
+ c0c25a82892b4418 v19.d[0] (xor, xfer vecreg #3)
+ 20c2fc8eb7ad7759 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.16b, v19.16b}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 46d75ee10e50be09 v18.d[0] (xor, xfer vecreg #2)
+ 994cc14d4dc6d220 v18.d[1] (xor, xfer vecreg #2)
+ 969f2359b0eb186b v19.d[0] (xor, xfer vecreg #3)
+ 32b896c1705b24b2 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.16b, v19.16b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ a6672f4bcbec37f6 v18.d[0] (xor, xfer vecreg #2)
+ 7450e1a0dd2c875c v18.d[1] (xor, xfer vecreg #2)
+ 8c0e66b914290533 v19.d[0] (xor, xfer vecreg #3)
+ 67572f0b71027756 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.8b, v19.8b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ ea98b281313421cb v18.d[0] (xor, xfer vecreg #2)
+ e6c4ce573a77bfb9 v18.d[1] (xor, xfer vecreg #2)
+ 5613a66010db7c60 v19.d[0] (xor, xfer vecreg #3)
+ 3a81956e994bcf77 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.8b, v19.8b}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ cf5562a648136f14 v18.d[0] (xor, xfer vecreg #2)
+ 7d8cc7c12bd9d151 v18.d[1] (xor, xfer vecreg #2)
+ be735c3995e0589e v19.d[0] (xor, xfer vecreg #3)
+ 783a100b63a9af60 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.8b, v19.8b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ decc42007498c7bf v18.d[0] (xor, xfer vecreg #2)
+ c397656ae2a55c5c v18.d[1] (xor, xfer vecreg #2)
+ 416bc056bf64fd24 v19.d[0] (xor, xfer vecreg #3)
+ cba20805b6be3db9 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LD3/ST3 (multiple 3-elem structs to/from 3 regs
+st3 {v17.2d, v18.2d, v19.2d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 0b a1 c8 ad f8 46 cd b5 91 b2 ac a8 2a 8f 92
+ [160] 64 f2 dc eb 72 a2 cf 3a ea 21 c1 53 f1 d5 85 47
+ [176] 01 51 60 3c 54 46 dc ad a1 cb c0 95 2b 55 23 db
+ [192] d8 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.2d, v18.2d, v19.2d}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 52 b1 73 83 ac fb 7e
+ [144] 9e d2 85 04 88 bf 16 3f d9 30 b7 55 77 8d be 41
+ [160] 3e 37 ff f0 7a 11 c9 50 3f 07 a8 69 3b 3e 61 a4
+ [176] e3 11 a9 53 d2 4e 34 9b 17 .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.2d, v18.2d, v19.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. ba 29 24 98 09 69 2a ae d7 ed ad 7a bd
+ [128] 70 ac 7a 42 73 4d 2d ab 3f ec 8d 69 8f 60 d8 c0
+ [144] 18 ef 14 af c7 f1 90 6f 6a ee 2d 16 2e e5 cd e0
+ [160] 72 cf c6 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.4s, v18.4s, v19.4s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. fb 1f 34 89 d2 87 05 28 a3 e1 da 63 db ba 7c
+ [160] 30 e7 73 96 15 16 18 b7 1e 8d c3 b5 9c 79 e4 09
+ [176] ba 1f 76 c3 f5 6c 3b c7 c1 7a 2d 56 ea cf 7c ca
+ [192] 09 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.4s, v18.4s, v19.4s}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. ef 45 99 4f 71 91 5f
+ [144] dc ba 10 99 a5 6f be 68 5a 07 fd 5f 2c 89 98 8e
+ [160] 45 7e e7 09 5d fc 80 e3 0e ea 0e 28 01 b5 c8 f8
+ [176] 86 67 13 2c 38 3a 7a 74 cd .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.4s, v18.4s, v19.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. e7 2c 25 cd 39 ae e7 cc 6a db e0 bd 6f
+ [128] b9 08 f6 1a 3e ae c9 8b 34 22 38 c2 be cf 88 ac
+ [144] 40 91 6c d4 6a 70 c5 c7 26 20 70 f9 5b db 51 8a
+ [160] 0d 8b f1 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.2s, v18.2s, v19.2s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 83 60 17 b5 fa fb db b9 b4 6e de 52 4a cf ca
+ [160] 75 43 76 02 e6 15 d8 30 06 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.2s, v18.2s, v19.2s}, [x5], #24 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. c2 c9 7f 22 cf 50 ec
+ [144] 32 04 04 b0 da 6d 32 33 ed 2a 9d f9 91 81 a7 70
+ [160] c7 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.2s, v18.2s, v19.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 4a 49 bb 50 95 a8 76 d8 3a a9 f0 4a e1
+ [128] ac a4 41 ec ea 20 ea f0 24 2d a2 .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.8h, v18.8h, v19.8h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 80 a4 a8 57 9c 59 7f 6f d2 fb f4 50 11 a3 e9
+ [160] f6 7d 63 5c 08 11 31 c5 24 0a d2 b4 54 c8 1b 89
+ [176] d2 a2 b1 29 15 2d 1e fc 83 a1 d8 65 06 cd 44 60
+ [192] eb .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.8h, v18.8h, v19.8h}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 2b fc 29 15 c5 d3 4a
+ [144] 2c b5 7b 41 73 14 81 74 1e b1 32 22 5b ff 0d 86
+ [160] c2 31 68 63 80 e5 0d 66 ef a5 f7 25 5d 6c 2c d4
+ [176] 46 a1 db 6c b0 67 3d 46 28 .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.8h, v18.8h, v19.8h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 21 a1 d7 0e 34 bf c2 7c ce 46 68 bc 6d
+ [128] 0b 78 4e b7 4e 0c 92 e2 6b 8e 2b 2d 03 c4 d9 79
+ [144] 54 ac bf 3b 21 ce ba 0f c5 88 f4 2b c2 c4 23 d9
+ [160] 22 bf ff .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.4h, v18.4h, v19.4h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. d2 29 65 d9 6b 11 54 46 6c 33 3c dd 0f 79 e3
+ [160] 70 94 5c 70 f4 38 48 96 f8 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.4h, v18.4h, v19.4h}, [x5], #24 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 8d 9e de 43 72 6e b0
+ [144] 65 37 ea ed 6f c4 70 84 9f 36 61 01 35 e9 4f 72
+ [160] 37 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.4h, v18.4h, v19.4h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. ad 53 07 d9 78 .. 15 c6 6d ca c7 73 53
+ [128] f6 d2 90 ce 9c f3 2d b5 fc c3 32 .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 5b f5 96 38 74 cd 80 d7 db 4e 48 79 24 de 71
+ [160] d5 0e 60 be 50 43 cd 37 .. 35 b2 c1 8a 79 03 44
+ [176] 9f ad 5b a7 cb a6 c7 49 76 5b 25 02 6e 7e dd 65
+ [192] 7a .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.16b, v18.16b, v19.16b}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 44 f9 ec 5a 54 cb 06
+ [144] ae 59 84 6a d0 dc d9 32 16 bd c7 61 3c 56 20 69
+ [160] 27 97 d8 e8 c6 af d1 2f f0 e7 d4 13 21 9e 28 ab
+ [176] 9e 7b ff ff 60 08 68 d1 c3 .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.16b, v18.16b, v19.16b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 2d 21 df c3 68 78 87 a0 3e e2 d6 cd d4
+ [128] 4f 22 4e a6 dc 80 01 37 10 e4 18 e1 df e4 52 c2
+ [144] 61 45 e9 05 67 f2 ba b9 66 b6 24 92 6e e1 0b 9b
+ [160] 55 10 80 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.8b, v18.8b, v19.8b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. f9 dc 4c 25 64 8d 62 13 07 24 9e a5 32 30 f1
+ [160] 67 31 6d a3 d4 d3 be 92 bd .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.8b, v18.8b, v19.8b}, [x5], #24 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. b2 41 b3 7f ef 68 2c
+ [144] b0 06 7e 35 94 be ef e0 fb 78 e4 23 89 41 e6 3a
+ [160] 90 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.8b, v18.8b, v19.8b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. e1 4a ef 56 6c 08 da 48 a9 e8 57 2d 2f
+ [128] c1 ee ee 64 ee 74 01 75 07 54 3d .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.2d, v18.2d, v19.2d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 2d3faa0dc364fe94 v17.d[0] (xor, xfer vecreg #1)
+ 88387ae0e7221a30 v17.d[1] (xor, xfer vecreg #1)
+ f8458a1f82380056 v18.d[0] (xor, xfer vecreg #2)
+ 96ba1ba260d0af61 v18.d[1] (xor, xfer vecreg #2)
+ 57742ff0e2139144 v19.d[0] (xor, xfer vecreg #3)
+ f428aa3dcb0ed1cb v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.2d, v18.2d, v19.2d}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 774a86e91f5fadf8 v17.d[0] (xor, xfer vecreg #1)
+ 0dc9208f66296ab0 v17.d[1] (xor, xfer vecreg #1)
+ 37efe2292e750afe v18.d[0] (xor, xfer vecreg #2)
+ de6bf343474d28fc v18.d[1] (xor, xfer vecreg #2)
+ 95b6fc4e0a4121ed v19.d[0] (xor, xfer vecreg #3)
+ e131b53ad6b1b1e5 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.2d, v18.2d, v19.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 24ca6f1117eb5a7d v17.d[0] (xor, xfer vecreg #1)
+ 4cea9f43e32a5060 v17.d[1] (xor, xfer vecreg #1)
+ dea66da250062733 v18.d[0] (xor, xfer vecreg #2)
+ 4cce89c5bae3f6f4 v18.d[1] (xor, xfer vecreg #2)
+ 01e1740747c4a942 v19.d[0] (xor, xfer vecreg #3)
+ 8c088b503a15d685 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.4s, v18.4s, v19.4s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ b16654fbb6532e0a v17.d[0] (xor, xfer vecreg #1)
+ 8c9e30a10f5e8472 v17.d[1] (xor, xfer vecreg #1)
+ 106896883ef86545 v18.d[0] (xor, xfer vecreg #2)
+ e720d0f77e8c8962 v18.d[1] (xor, xfer vecreg #2)
+ aece256f683ebe23 v19.d[0] (xor, xfer vecreg #3)
+ 12e8a4f411d8f102 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.4s, v18.4s, v19.4s}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 8b5476e5847683f7 v17.d[0] (xor, xfer vecreg #1)
+ b09777e38635d9d0 v17.d[1] (xor, xfer vecreg #1)
+ 83dfaecfc9b9c1e0 v18.d[0] (xor, xfer vecreg #2)
+ d2ef4ccbfc88b738 v18.d[1] (xor, xfer vecreg #2)
+ 503955345a56b2e2 v19.d[0] (xor, xfer vecreg #3)
+ 84f804e2eadf0605 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.4s, v18.4s, v19.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 735de39a45a32039 v17.d[0] (xor, xfer vecreg #1)
+ c6dd5953e234d8cb v17.d[1] (xor, xfer vecreg #1)
+ 135e647bfd30f538 v18.d[0] (xor, xfer vecreg #2)
+ 715407d427e8720a v18.d[1] (xor, xfer vecreg #2)
+ 4516a0c6fcfa1126 v19.d[0] (xor, xfer vecreg #3)
+ d6cb7312471fd57a v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.2s, v18.2s, v19.2s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 803c941aa5e8ac15 v17.d[0] (xor, xfer vecreg #1)
+ 4e1e7b0f68a4eaef v17.d[1] (xor, xfer vecreg #1)
+ 4f60485893954416 v18.d[0] (xor, xfer vecreg #2)
+ 190aec8d9ee8e9d7 v18.d[1] (xor, xfer vecreg #2)
+ 32b6dec8811a2fa3 v19.d[0] (xor, xfer vecreg #3)
+ 59d0ac9ab1b7c699 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.2s, v18.2s, v19.2s}, [x5], #24 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ dbe2906a92d6be3a v17.d[0] (xor, xfer vecreg #1)
+ 6c0e0fc546956b0e v17.d[1] (xor, xfer vecreg #1)
+ c3ec56b77fef30cf v18.d[0] (xor, xfer vecreg #2)
+ b929d64dde033b8e v18.d[1] (xor, xfer vecreg #2)
+ e892cbd65a46a7a3 v19.d[0] (xor, xfer vecreg #3)
+ 94c32d11fdf03864 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.2s, v18.2s, v19.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 3faa25263e04b54f v17.d[0] (xor, xfer vecreg #1)
+ 4bebac731a38e7fa v17.d[1] (xor, xfer vecreg #1)
+ 0514cbbaaf35b64e v18.d[0] (xor, xfer vecreg #2)
+ 00231fa35a9f3c8f v18.d[1] (xor, xfer vecreg #2)
+ 64c9f1763a5bf0ba v19.d[0] (xor, xfer vecreg #3)
+ dcffe33c4afa9177 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.8h, v18.8h, v19.8h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 4b5e8c99b4b2415a v17.d[0] (xor, xfer vecreg #1)
+ 780d30df8f50a9d0 v17.d[1] (xor, xfer vecreg #1)
+ 4ebaf1d0f61572e4 v18.d[0] (xor, xfer vecreg #2)
+ 5029c936cf63c647 v18.d[1] (xor, xfer vecreg #2)
+ 44b0070d18374c3b v19.d[0] (xor, xfer vecreg #3)
+ 36f5fe1daa614fed v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.8h, v18.8h, v19.8h}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 88841e664aee9633 v17.d[0] (xor, xfer vecreg #1)
+ aa955b25cb24d99b v17.d[1] (xor, xfer vecreg #1)
+ 1052ded67eff9950 v18.d[0] (xor, xfer vecreg #2)
+ 8eb051222088d43a v18.d[1] (xor, xfer vecreg #2)
+ 1a8f821d92d5a829 v19.d[0] (xor, xfer vecreg #3)
+ 41db8f01cdbeff00 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.8h, v18.8h, v19.8h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 6f5e193b56622541 v17.d[0] (xor, xfer vecreg #1)
+ 38002d324c5e2378 v17.d[1] (xor, xfer vecreg #1)
+ 54c4d4b0cf1a50b9 v18.d[0] (xor, xfer vecreg #2)
+ 66b59229204aa411 v18.d[1] (xor, xfer vecreg #2)
+ cc83ea85a731b5cb v19.d[0] (xor, xfer vecreg #3)
+ 9e9948c68f762904 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.4h, v18.4h, v19.4h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 8a3b669d76e2280a v17.d[0] (xor, xfer vecreg #1)
+ 9ea5457459da6833 v17.d[1] (xor, xfer vecreg #1)
+ a759d5fac3ddb273 v18.d[0] (xor, xfer vecreg #2)
+ f09cc471f72df209 v18.d[1] (xor, xfer vecreg #2)
+ 776849cca2cf9805 v19.d[0] (xor, xfer vecreg #3)
+ cdcc978ae949c027 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.4h, v18.4h, v19.4h}, [x5], #24 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 194f3a08cbbac75f v17.d[0] (xor, xfer vecreg #1)
+ 3c69692ab80ce208 v17.d[1] (xor, xfer vecreg #1)
+ 4a8c4924a068df7a v18.d[0] (xor, xfer vecreg #2)
+ 752442e55d5d8069 v18.d[1] (xor, xfer vecreg #2)
+ 4c4ab284d9277688 v19.d[0] (xor, xfer vecreg #3)
+ 51bcb069ff6cb390 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.4h, v18.4h, v19.4h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 3d9dcdfbefd6b64c v17.d[0] (xor, xfer vecreg #1)
+ 34d1ed5126282ea1 v17.d[1] (xor, xfer vecreg #1)
+ aa4bcbca2496574c v18.d[0] (xor, xfer vecreg #2)
+ 393d76681846960c v18.d[1] (xor, xfer vecreg #2)
+ 428cd7af9ba7dc0b v19.d[0] (xor, xfer vecreg #3)
+ 7bab55752f966438 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 2f9e965821b52f76 v17.d[0] (xor, xfer vecreg #1)
+ 6ead20a428075a81 v17.d[1] (xor, xfer vecreg #1)
+ 4d500c86c51fe7ec v18.d[0] (xor, xfer vecreg #2)
+ 9a181bf39dae3ce5 v18.d[1] (xor, xfer vecreg #2)
+ 07c3f0777fb6a1a0 v19.d[0] (xor, xfer vecreg #3)
+ 4eb9dd7d32fc84f3 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.16b, v18.16b, v19.16b}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 79d3ab828f65b1cd v17.d[0] (xor, xfer vecreg #1)
+ 836d5fa616c51d0f v17.d[1] (xor, xfer vecreg #1)
+ 6a6d1ddbbc0a5208 v18.d[0] (xor, xfer vecreg #2)
+ 30ff03d917311c32 v18.d[1] (xor, xfer vecreg #2)
+ 1b39f791acad92c9 v19.d[0] (xor, xfer vecreg #3)
+ ca4bd2643f40bd4e v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.16b, v18.16b, v19.16b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 64bb874258232194 v17.d[0] (xor, xfer vecreg #1)
+ 2332c7b1d4b4a960 v17.d[1] (xor, xfer vecreg #1)
+ e19ef568b134ee2b v18.d[0] (xor, xfer vecreg #2)
+ 372b42a3fb37b228 v18.d[1] (xor, xfer vecreg #2)
+ 40cbb2cf2e8d6615 v19.d[0] (xor, xfer vecreg #3)
+ 426df11fc331ac35 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.8b, v18.8b, v19.8b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 7b2f0b2ff6f1d93c v17.d[0] (xor, xfer vecreg #1)
+ dbea95e3bddd6240 v17.d[1] (xor, xfer vecreg #1)
+ ea5a8b3ae782cb00 v18.d[0] (xor, xfer vecreg #2)
+ 0d6639969d370fbb v18.d[1] (xor, xfer vecreg #2)
+ 5d692c7179f4451b v19.d[0] (xor, xfer vecreg #3)
+ e07837f4469865ee v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.8b, v18.8b, v19.8b}, [x5], #24 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ ada377ebb977144f v17.d[0] (xor, xfer vecreg #1)
+ 8bd358692f9fe49a v17.d[1] (xor, xfer vecreg #1)
+ efbc3776ae301641 v18.d[0] (xor, xfer vecreg #2)
+ 07a55a8fb9cce995 v18.d[1] (xor, xfer vecreg #2)
+ 3ba157ca3fcdd2a3 v19.d[0] (xor, xfer vecreg #3)
+ 3db3f80bb6f4e9c3 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.8b, v18.8b, v19.8b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ f6d2a1b67f9c7190 v17.d[0] (xor, xfer vecreg #1)
+ 2c17d4d8c78510b0 v17.d[1] (xor, xfer vecreg #1)
+ 264479c7969336e5 v18.d[0] (xor, xfer vecreg #2)
+ d82e8a0e425124a9 v18.d[1] (xor, xfer vecreg #2)
+ 64296b0536be31bd v19.d[0] (xor, xfer vecreg #3)
+ d8a69cc8588f02d1 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LD4/ST4 (multiple 4-elem structs to/from 4 regs
+st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. f8 ae 93 20 0e ce 21 6f d6 44 c2 10 55 18 13
+ [160] 5b 91 16 73 c4 cb 40 37 19 8e e1 b0 13 9d 04 b4
+ [176] f4 06 13 92 48 2c 9a 8d 56 25 60 82 8c 6f 5a a3
+ [192] 7a ba 88 9b 1f 15 71 27 d3 f4 f2 ee c1 8d c3 cb
+ [208] 14 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. d7 eb 5d 89 6f dc ad
+ [144] 84 f5 3c 7b c7 34 66 f4 79 a2 fc ad 54 4f 55 fc
+ [160] 03 9d 3c e9 a8 e6 d6 77 2e d1 45 5e c4 21 9a 44
+ [176] c4 02 3b d6 74 71 56 e3 3a a5 e9 90 e6 11 17 88
+ [192] 10 3e 07 8b 7b 6f 33 6f bd .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. e9 29 d9 a4 f3 60 2d a4 53 88 2c e6 6b
+ [128] ae a4 99 22 4d f1 11 5b 72 9c 37 eb 49 7e fa ba
+ [144] 32 e2 3e .. 0f e7 89 f2 2d 02 f1 cb ab 2a ff 71
+ [160] 07 2f a4 3a fa 9b 46 a0 5b 8f a1 6b 37 5a e0 7d
+ [176] 9a 3a d2 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. ba 8f 64 5c eb c9 08 ee fb 54 09 cd 5d 9d 5b
+ [160] 47 4d 24 72 66 35 32 f3 7e ee 3b 87 61 ca 16 4b
+ [176] 26 af cf 38 31 26 81 70 0c 55 3f 0f f6 ec c9 dd
+ [192] 4b 74 b2 53 ee 95 d4 8e 3e d7 e7 59 55 8a cf 6d
+ [208] 15 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 92 d8 67 1d a6 25 b3
+ [144] 73 d1 01 1a 11 e8 74 94 e1 d5 63 83 8c 43 e8 3b
+ [160] 33 96 3f 66 64 53 69 79 de 9c 7b f4 85 3f d8 bd
+ [176] 72 8b af f0 ee 34 7d .. 0d 22 94 dc 7e a2 d6 c4
+ [192] bc 92 8d 67 82 14 ef 73 7a .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. b6 fc f4 ba 5e de a4 11 c2 1b 62 44 59
+ [128] df fb bb 1a 9b 96 2d 0f 6e 65 46 b9 7f 0e ea 3f
+ [144] 40 32 85 8a a1 38 28 6d da 90 8f 25 09 dc e4 01
+ [160] 69 17 15 70 da 85 f1 f7 8d f6 a8 27 34 fd 14 bb
+ [176] 0c 2b e7 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 52 b2 6d e7 f0 88 57 30 c8 66 6b 0e 97 5b 02
+ [160] ac c4 95 ef 6c 43 2c e3 d8 37 50 de 93 02 3d 26
+ [176] 52 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. c5 34 f0 b6 90 06 98
+ [144] bf e4 2f cd bd 87 7c 91 94 fa 2a 36 fd 10 49 7b
+ [160] 5c 4c 5e 53 af de ef f9 6c .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 37 a8 a2 5d 0d 17 48 16 aa 2a 95 73 6c
+ [128] 6a 13 31 eb 06 c0 47 cc 31 35 6c 1b 9f a7 02 a2
+ [144] df 38 88 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 9f 59 7c 11 3d d2 5c a1 f0 74 87 7c 9e ae 6c
+ [160] e3 8d 1c 32 46 0b 1c 6f 75 07 0f af f1 3c ca e8
+ [176] 78 e2 09 5b 17 37 41 d3 f5 bb ea 5c 44 8f 4f 3f
+ [192] 2d 20 bf 0d 4f 56 87 4f e8 7f db 21 cc e7 ab d4
+ [208] d6 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. cc c0 ab 2b b4 ee c9
+ [144] ce 32 5d af 2d f6 e9 8c fe 14 33 ef 63 03 1e ef
+ [160] 3c 59 c4 8c 91 94 74 17 5a 73 b4 ea 5d 14 e8 fd
+ [176] 78 1d 0f 66 45 67 f8 18 50 3e fa 89 f1 df 0c 23
+ [192] b8 dc 60 38 0c 21 ef cb e6 .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. ae 4f 57 90 b7 96 7c 79 3c 0a bb 6a 92
+ [128] fe 8f ab fd ee 78 f6 72 fb f7 2f 9d 66 01 a0 dd
+ [144] 3f f4 27 98 d1 e1 3f 18 8d b5 2b 42 49 1e 6a 2a
+ [160] 6b a8 cb 2a cf bd b3 4c 54 7c 3c 1b c9 fb 03 f0
+ [176] 75 06 96 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 82 c1 5b f6 e5 c1 59 bd 39 01 7e 2b a8 cb 7a
+ [160] 2f 49 b8 10 32 b6 54 6a c8 41 e5 13 07 6e bf 2f
+ [176] 99 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 0c 3b 41 64 e7 97 66
+ [144] a9 5a 29 f2 82 04 ce e3 e1 41 ff 7d d1 b6 75 2b
+ [160] 06 b4 d3 e2 db 72 74 f3 27 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 58 10 9c 7f cb 84 13 1d 3b c4 60 36 33
+ [128] 0a af 4a 51 35 ac 6e 30 9e 40 dc 22 6e a5 6b d0
+ [144] 07 66 41 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. db ea 35 91 65 c3 5a 17 dc 19 02 04 f2 cb 33
+ [160] cc 99 5b 0c b8 ce 0c f8 5c c8 14 98 79 c5 75 13
+ [176] b3 bf 52 5f ba 2c af 57 80 04 a8 fd 45 3c ad b3
+ [192] 5f ae 9c 2e ef 98 cf c1 7b e6 88 b3 84 78 d0 16
+ [208] 43 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. e2 3b 89 d1 3e 14 90
+ [144] e6 be 62 cb 52 6c 77 bf fa a3 73 95 c0 10 cb e0
+ [160] b6 bc 45 43 ba 03 ab 49 53 7a 85 0d f5 83 fa b6
+ [176] f4 a6 8b f6 ea 6b 34 a7 75 bf 80 f8 1f d2 18 60
+ [192] ce a5 75 2c 80 d6 e5 36 91 .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 77 6d f7 05 e0 75 b1 39 eb 3d 96 7b 5d
+ [128] 32 97 2e e8 87 93 7f ad c0 89 74 fa 7a 46 b4 b7
+ [144] 86 90 b7 4e aa 85 2d 23 ec 0a 70 e8 a9 b0 c4 ad
+ [160] cb 0a 96 7f 3d 47 85 d9 87 a2 bc 59 d2 68 60 64
+ [176] b3 6c 7a .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 89 0c 8b f3 23 2b 18 8e 9b 85 6e 85 8e 64 25
+ [160] fb 1c 33 ba fa ee 7b 21 d2 1c 8b fe 1f 0f 7d 2b
+ [176] c8 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. af 16 ad e8 d9 92 44
+ [144] e5 9e 21 2b 1e dd 65 62 0b 59 a6 ac 8e 63 96 1a
+ [160] 6c 73 9f e1 ec 95 2a c8 5e .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 4b 3f 18 6e 2c 66 53 8d 6e 7b 65 86 e6
+ [128] 96 b8 75 c0 4c 9d 79 16 c8 9f 77 07 d3 42 c8 09
+ [144] dc 24 6a .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 7cdc6a4cb1ca0db2 v17.d[0] (xor, xfer vecreg #1)
+ f6e07024bc2bbac8 v17.d[1] (xor, xfer vecreg #1)
+ d10659592ddac3df v18.d[0] (xor, xfer vecreg #2)
+ 35460a7dc7b61cdb v18.d[1] (xor, xfer vecreg #2)
+ aae6ffca9c8ef313 v19.d[0] (xor, xfer vecreg #3)
+ cef5c9f680efb52a v19.d[1] (xor, xfer vecreg #3)
+ 5ae2309242f7e39b v20.d[0] (xor, xfer vecreg #3)
+ bcc2b1b23915089d v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 975f399d84853532 v17.d[0] (xor, xfer vecreg #1)
+ 3649318a4ab0f9b0 v17.d[1] (xor, xfer vecreg #1)
+ e095b3ade6f66600 v18.d[0] (xor, xfer vecreg #2)
+ ea7a0f445b58ab86 v18.d[1] (xor, xfer vecreg #2)
+ 2ccd5c9917f659a6 v19.d[0] (xor, xfer vecreg #3)
+ 936f7c445ca6136e v19.d[1] (xor, xfer vecreg #3)
+ 3f4df0654a6bdbbf v20.d[0] (xor, xfer vecreg #3)
+ bcc6876800bb3d8f v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 74d227b28ef5deec v17.d[0] (xor, xfer vecreg #1)
+ efa61ef3f8962f58 v17.d[1] (xor, xfer vecreg #1)
+ 0642e77bbbebb12a v18.d[0] (xor, xfer vecreg #2)
+ 25d343fe2fd4e718 v18.d[1] (xor, xfer vecreg #2)
+ 312b520843349660 v19.d[0] (xor, xfer vecreg #3)
+ d9ea3254ece3c2af v19.d[1] (xor, xfer vecreg #3)
+ 5f00d35c0339790d v20.d[0] (xor, xfer vecreg #3)
+ b0e56651c8286acb v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ e259fbcbc5da079b v17.d[0] (xor, xfer vecreg #1)
+ 47e0a998934bf604 v17.d[1] (xor, xfer vecreg #1)
+ b9a7fcaf656c89ee v18.d[0] (xor, xfer vecreg #2)
+ 9f4c9acd399de975 v18.d[1] (xor, xfer vecreg #2)
+ 453f2c20d0e477f4 v19.d[0] (xor, xfer vecreg #3)
+ a93f422addfb09bb v19.d[1] (xor, xfer vecreg #3)
+ 7f0751cd129f268b v20.d[0] (xor, xfer vecreg #3)
+ 5a322a7d9c09f0fd v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 43d051c257f08454 v17.d[0] (xor, xfer vecreg #1)
+ c2a8435796845c93 v17.d[1] (xor, xfer vecreg #1)
+ 1a9cbe5362b9c17d v18.d[0] (xor, xfer vecreg #2)
+ d57cc96d2422a46a v18.d[1] (xor, xfer vecreg #2)
+ 21566d530547dff2 v19.d[0] (xor, xfer vecreg #3)
+ 07b2e71d95b10f0d v19.d[1] (xor, xfer vecreg #3)
+ f0532e871ce7bdb0 v20.d[0] (xor, xfer vecreg #3)
+ fe054cb94e8fbd3b v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 1ff18949dc67ac30 v17.d[0] (xor, xfer vecreg #1)
+ 020f91cca192812c v17.d[1] (xor, xfer vecreg #1)
+ 5802a57abe6040ba v18.d[0] (xor, xfer vecreg #2)
+ c583ebbbf51b1053 v18.d[1] (xor, xfer vecreg #2)
+ a8a22e0874fadae1 v19.d[0] (xor, xfer vecreg #3)
+ 0d64eeee8f2165ed v19.d[1] (xor, xfer vecreg #3)
+ 0356ad4ad0af35cd v20.d[0] (xor, xfer vecreg #3)
+ e7f5ddda8306dcca v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ e86e7e3889d6fff7 v17.d[0] (xor, xfer vecreg #1)
+ 27171442a58d9cd3 v17.d[1] (xor, xfer vecreg #1)
+ 855b43d26343ae1e v18.d[0] (xor, xfer vecreg #2)
+ df2ddbce7293df55 v18.d[1] (xor, xfer vecreg #2)
+ 1f266cfc9e63bc8c v19.d[0] (xor, xfer vecreg #3)
+ a6af1aca57d6cab3 v19.d[1] (xor, xfer vecreg #3)
+ e0c27be8980ea2ce v20.d[0] (xor, xfer vecreg #3)
+ 0175939ab026b609 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ f5b16fb7ef4413a5 v17.d[0] (xor, xfer vecreg #1)
+ 9c62e60ae1d339f8 v17.d[1] (xor, xfer vecreg #1)
+ c0b2b747d949fc44 v18.d[0] (xor, xfer vecreg #2)
+ 92b31e8c8dd028bd v18.d[1] (xor, xfer vecreg #2)
+ 1d7753756ad16bf9 v19.d[0] (xor, xfer vecreg #3)
+ b015102bf9fe10db v19.d[1] (xor, xfer vecreg #3)
+ 48f902b29ae51349 v20.d[0] (xor, xfer vecreg #3)
+ bca0bd8bc36d8aaf v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 7203b32d3ff5c083 v17.d[0] (xor, xfer vecreg #1)
+ faa12713bb55b8b1 v17.d[1] (xor, xfer vecreg #1)
+ c09fea2094902984 v18.d[0] (xor, xfer vecreg #2)
+ 151b28288c150a37 v18.d[1] (xor, xfer vecreg #2)
+ be7fd8154c4a5acd v19.d[0] (xor, xfer vecreg #3)
+ f0cba389457d2514 v19.d[1] (xor, xfer vecreg #3)
+ 6e5e8e711c5ae947 v20.d[0] (xor, xfer vecreg #3)
+ 9209da17c6dbe3e2 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 91acd27888de2c67 v17.d[0] (xor, xfer vecreg #1)
+ 2e98c859e935f52a v17.d[1] (xor, xfer vecreg #1)
+ 308c4715ab0180b6 v18.d[0] (xor, xfer vecreg #2)
+ f1aba85fd116b00e v18.d[1] (xor, xfer vecreg #2)
+ f6e69168ab9e7db4 v19.d[0] (xor, xfer vecreg #3)
+ 2bafa8fa627f9052 v19.d[1] (xor, xfer vecreg #3)
+ e3cc13789e4129d6 v20.d[0] (xor, xfer vecreg #3)
+ 6dbd9f1450e6715f v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 9b69380ced024d0b v17.d[0] (xor, xfer vecreg #1)
+ d461b3541ef78589 v17.d[1] (xor, xfer vecreg #1)
+ 1baad8877baf9719 v18.d[0] (xor, xfer vecreg #2)
+ abbce06b64e55c19 v18.d[1] (xor, xfer vecreg #2)
+ 83997593d18c2b89 v19.d[0] (xor, xfer vecreg #3)
+ 75178c6e5dc7da73 v19.d[1] (xor, xfer vecreg #3)
+ 42cb0d681a8a0f00 v20.d[0] (xor, xfer vecreg #3)
+ 4d3a183ad0820861 v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ e9c28ab7ec5247aa v17.d[0] (xor, xfer vecreg #1)
+ 3546c46036a70c18 v17.d[1] (xor, xfer vecreg #1)
+ 30650bc6500457f3 v18.d[0] (xor, xfer vecreg #2)
+ d3413b0b68aeb913 v18.d[1] (xor, xfer vecreg #2)
+ 75aa1eb2d8b68704 v19.d[0] (xor, xfer vecreg #3)
+ e1cbecbde6602f30 v19.d[1] (xor, xfer vecreg #3)
+ 3b00526b0c113d55 v20.d[0] (xor, xfer vecreg #3)
+ 60b62dd0ee5c2f58 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ dd5ea9fc50d26698 v17.d[0] (xor, xfer vecreg #1)
+ db36644ca4bd5aef v17.d[1] (xor, xfer vecreg #1)
+ 033c9c1d8535794f v18.d[0] (xor, xfer vecreg #2)
+ 82a0e1dec29b5066 v18.d[1] (xor, xfer vecreg #2)
+ a587720d1a5ec0b0 v19.d[0] (xor, xfer vecreg #3)
+ 4fd3db6f6ef35328 v19.d[1] (xor, xfer vecreg #3)
+ f5d6509442c84317 v20.d[0] (xor, xfer vecreg #3)
+ 462995e284163ed0 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ a0d529c82a33cd44 v17.d[0] (xor, xfer vecreg #1)
+ c18535c552746079 v17.d[1] (xor, xfer vecreg #1)
+ 94af0daad0114360 v18.d[0] (xor, xfer vecreg #2)
+ 0bbe2701f31c4628 v18.d[1] (xor, xfer vecreg #2)
+ 0fa2f1afee6aebe0 v19.d[0] (xor, xfer vecreg #3)
+ 9365d9e8ca338a9e v19.d[1] (xor, xfer vecreg #3)
+ 24d8ca2d602aec7d v20.d[0] (xor, xfer vecreg #3)
+ 9e14cb9ff54a47b7 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 9d156f3883b047c0 v17.d[0] (xor, xfer vecreg #1)
+ 2880cff6b69e1f8f v17.d[1] (xor, xfer vecreg #1)
+ 0da71bcb793cd110 v18.d[0] (xor, xfer vecreg #2)
+ fa768c7a20deabf3 v18.d[1] (xor, xfer vecreg #2)
+ f3bb2d0a8cfbeb09 v19.d[0] (xor, xfer vecreg #3)
+ a3ffcbd6e803671c v19.d[1] (xor, xfer vecreg #3)
+ 3c75d468e89fd14b v20.d[0] (xor, xfer vecreg #3)
+ a9f54b6f6edcac25 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 69efc1e3a5a95bda v17.d[0] (xor, xfer vecreg #1)
+ 424d2ede106d3d79 v17.d[1] (xor, xfer vecreg #1)
+ 56d0a9fc3bd63558 v18.d[0] (xor, xfer vecreg #2)
+ 97a9aff44b8825ce v18.d[1] (xor, xfer vecreg #2)
+ 80c13e3e84fae418 v19.d[0] (xor, xfer vecreg #3)
+ e10f2942d97e4890 v19.d[1] (xor, xfer vecreg #3)
+ 4520747b1c435751 v20.d[0] (xor, xfer vecreg #3)
+ fc8f98f1d6001e87 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 80001c8b2df94eb9 v17.d[0] (xor, xfer vecreg #1)
+ f146b912f8e333b5 v17.d[1] (xor, xfer vecreg #1)
+ 03dea227c83d35e3 v18.d[0] (xor, xfer vecreg #2)
+ 9d599cbaf2e281f1 v18.d[1] (xor, xfer vecreg #2)
+ 79b858b901e852b1 v19.d[0] (xor, xfer vecreg #3)
+ fe84453eef3ee772 v19.d[1] (xor, xfer vecreg #3)
+ 1f7cd96cc2e165de v20.d[0] (xor, xfer vecreg #3)
+ c01c3525dc0ef872 v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 92af5dc4bc416817 v17.d[0] (xor, xfer vecreg #1)
+ 5dc3de198d6b5165 v17.d[1] (xor, xfer vecreg #1)
+ 9c1cf031d692e9e8 v18.d[0] (xor, xfer vecreg #2)
+ 9eb3569cc1006273 v18.d[1] (xor, xfer vecreg #2)
+ 01f8c477dcf36bf9 v19.d[0] (xor, xfer vecreg #3)
+ 80625d995d2c6b5b v19.d[1] (xor, xfer vecreg #3)
+ 9ca873685a1cf1c8 v20.d[0] (xor, xfer vecreg #3)
+ 9a1cbcc73677e106 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 9e7606541bd54130 v17.d[0] (xor, xfer vecreg #1)
+ 1d34da81b7da33f2 v17.d[1] (xor, xfer vecreg #1)
+ 0a1dc7bf4fe49bd0 v18.d[0] (xor, xfer vecreg #2)
+ 0c692351fe877418 v18.d[1] (xor, xfer vecreg #2)
+ 309222c9b19f58ef v19.d[0] (xor, xfer vecreg #3)
+ 36c7f1ae49ed28f6 v19.d[1] (xor, xfer vecreg #3)
+ b2af3bd3b6ad9dcc v20.d[0] (xor, xfer vecreg #3)
+ 212405fbf5daaaa8 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 85889e0b4c6196cd v17.d[0] (xor, xfer vecreg #1)
+ 04d6ba796752b1b2 v17.d[1] (xor, xfer vecreg #1)
+ e530795651334d12 v18.d[0] (xor, xfer vecreg #2)
+ fa6f7da8d59d2603 v18.d[1] (xor, xfer vecreg #2)
+ 2da7087d0d5f0962 v19.d[0] (xor, xfer vecreg #3)
+ 43d50610ef966089 v19.d[1] (xor, xfer vecreg #3)
+ 0fc46f4aed1bafc7 v20.d[0] (xor, xfer vecreg #3)
+ a61f5655534cf7a0 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ b4898b2386bc662e v17.d[0] (xor, xfer vecreg #1)
+ 05ddbba2e575c2f5 v17.d[1] (xor, xfer vecreg #1)
+ 91b1e118fbd9c66b v18.d[0] (xor, xfer vecreg #2)
+ e6c74ecdc02c21ef v18.d[1] (xor, xfer vecreg #2)
+ a6b0ca3fa5dfbe63 v19.d[0] (xor, xfer vecreg #3)
+ b5a2685e7006151c v19.d[1] (xor, xfer vecreg #3)
+ 50e1c12ce6386bc2 v20.d[0] (xor, xfer vecreg #3)
+ 76c74939d2527917 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LD1/ST1 (multiple 1-elem structs to/from 2/3/4 regs
+st1 {v19.16b, v20.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. ab d7 bd ea 5c d2 ef 93 ea 9e 58 ad 15 d3 6b
+ [160] 6f 92 04 a1 1e 4e 21 cf 3e 4d 6d cc c6 66 69 01
+ [176] 8f .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.16b, v20.16b}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. cc 79 aa 79 30 64 50
+ [144] 2a e9 a6 99 31 f0 0d 6b ac a1 02 22 80 7a 9a 59
+ [160] d8 8d 3c 3a c9 3f a1 e3 b8 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 42 2e 44 6a fb 83 b4 f8 8a c7 10 14 20 59 b0
+ [160] 05 87 6c 37 a4 c4 2d 54 60 57 58 a3 b8 3d 03 bd
+ [176] 2f 8a 69 10 f2 0f 3e 9d 59 1f 1e 07 f1 f1 a1 35
+ [192] 84 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.16b, v20.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 31a43e0a5e012507 v19.d[0] (xor, xfer vecreg #3)
+ ffc16831bac1764c v19.d[1] (xor, xfer vecreg #3)
+ ba5fe9de7f2bc566 v20.d[0] (xor, xfer vecreg #3)
+ 0b988387fa86a920 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.16b, v20.16b}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 924e806699528e97 v19.d[0] (xor, xfer vecreg #3)
+ 2d7a9db532e32205 v19.d[1] (xor, xfer vecreg #3)
+ 4d31cf518f003578 v20.d[0] (xor, xfer vecreg #3)
+ 4bcfc3df3ae33639 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 1633997eeefe0b8e v17.d[0] (xor, xfer vecreg #1)
+ ef6aaf66a48aef2a v17.d[1] (xor, xfer vecreg #1)
+ 8ad7739f4891d97f v18.d[0] (xor, xfer vecreg #2)
+ 90fcabef304aad06 v18.d[1] (xor, xfer vecreg #2)
+ 29487185424a39eb v19.d[0] (xor, xfer vecreg #3)
+ 5aed4c9ff73637b0 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LD1R (single structure, replicate)
+ld1r {v17.2d}, [x5] with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ e1f0837e84b68683 v17.d[0] (xor, xfer vecreg #1)
+ e9a6ec8cff7474b3 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.1d}, [x5] with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 1bc3341432dc6604 v17.d[0] (xor, xfer vecreg #1)
+ 64833826bd0baf0a v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.4s}, [x5] with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0a7c91ae32af6e7d v17.d[0] (xor, xfer vecreg #1)
+ 49a6c882c10e8cbf v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.2s}, [x5] with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ a5b299eb90f5790f v17.d[0] (xor, xfer vecreg #1)
+ cd4cb5e79a5bb831 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.8h}, [x5] with x5 = middle_of_block+3, x6=-1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ f7482086533cc722 v17.d[0] (xor, xfer vecreg #1)
+ f9df7b08611cc893 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.4h}, [x5] with x5 = middle_of_block+3, x6=1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 893ff710eff56429 v17.d[0] (xor, xfer vecreg #1)
+ 4995e4da614938d9 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.16b}, [x5] with x5 = middle_of_block+3, x6=2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 1a5fdd6af4164e63 v17.d[0] (xor, xfer vecreg #1)
+ 4f9c6e6fb16a7758 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.8b}, [x5] with x5 = middle_of_block+3, x6=3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 056cdcd43f5f808d v17.d[0] (xor, xfer vecreg #1)
+ f8fee69f317551a2 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.2d}, [x5], #8 with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 10cf519ed1f11fe7 v17.d[0] (xor, xfer vecreg #1)
+ 771a6a1970e4d881 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.1d}, [x5], #8 with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ f5050c8d137bfa17 v17.d[0] (xor, xfer vecreg #1)
+ fa27dad82a7f232c v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.4s}, [x5], #4 with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ ebe0cc912e044127 v17.d[0] (xor, xfer vecreg #1)
+ 93338793978fa5ca v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.2s}, [x5], #4 with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 237643f435a6133d v17.d[0] (xor, xfer vecreg #1)
+ 70afe1246d06cd17 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.8h}, [x5], #2 with x5 = middle_of_block+3, x6=-1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 800678a83fe98c73 v17.d[0] (xor, xfer vecreg #1)
+ 08d54d2ffc97a56e v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.4h}, [x5], #2 with x5 = middle_of_block+3, x6=1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ b1a8115281eeb40c v17.d[0] (xor, xfer vecreg #1)
+ 79381a2219ac6f02 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.16b}, [x5], #1 with x5 = middle_of_block+3, x6=2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 6d94b259250c504b v17.d[0] (xor, xfer vecreg #1)
+ d9988551a7caf1ed v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 1 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.8b}, [x5], #1 with x5 = middle_of_block+3, x6=3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 5ccf8332a7b6af5e v17.d[0] (xor, xfer vecreg #1)
+ 3660a5744f0f298f v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 1 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.2d}, [x5], x6 with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ f089b2feb2543ba0 v17.d[0] (xor, xfer vecreg #1)
+ f7f5f85088bff4cb v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.1d}, [x5], x6 with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 330bb577859e83d6 v17.d[0] (xor, xfer vecreg #1)
+ c6c8a3b82ed11c5c v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.4s}, [x5], x6 with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ f68a070e043e28c1 v17.d[0] (xor, xfer vecreg #1)
+ 07227f20e7c21d0a v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.2s}, [x5], x6 with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 5d921db2ee29bd8f v17.d[0] (xor, xfer vecreg #1)
+ 4910338fd690680b v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.8h}, [x5], x6 with x5 = middle_of_block+3, x6=-1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ d66c4e76b0aabf7c v17.d[0] (xor, xfer vecreg #1)
+ 1884040a48fe4126 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -1 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.4h}, [x5], x6 with x5 = middle_of_block+3, x6=1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 7748963dcf2b9583 v17.d[0] (xor, xfer vecreg #1)
+ e0d8759968ed2c3a v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 1 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.16b}, [x5], x6 with x5 = middle_of_block+3, x6=2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 5abea78a1d55be57 v17.d[0] (xor, xfer vecreg #1)
+ 39ca974096dcf130 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.8b}, [x5], x6 with x5 = middle_of_block+3, x6=3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 3ec4c291eadf5671 v17.d[0] (xor, xfer vecreg #1)
+ aac08a760388888a v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 3 x5 (sub, base reg)
0 x6 (sub, index reg)
+LD2R (single structure, replicate)
+LD4R (single structure, replicate)
+LD1/ST1 (single 1-elem struct to/from one lane of 1 reg
+LD2/ST2 (single 2-elem struct to/from one lane of 2 regs
+LD3/ST3 (single 3-elem struct to/from one lane of 3 regs
+LD4/ST4 (single 4-elem struct to/from one lane of 4 regs
projects / thirdparty / valgrind.git / commitdiff
