]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
media: chips-media: wave5: Support CBP profile
authorJackson Lee <jackson.lee@chipsnmedia.com>
Tue, 24 Mar 2026 05:03:59 +0000 (14:03 +0900)
committerHans Verkuil <hverkuil+cisco@kernel.org>
Mon, 4 May 2026 06:35:14 +0000 (08:35 +0200)
Constrained Baseline Profile (CBP) and Baseline Profile (BP) have been
treated as the same.
Introduce the ability to differentiate between the two.

Fixes: 9707a6254a8a ("media: chips-media: wave5: Add the v4l2 layer")
Cc: stable@vger.kernel.org
Signed-off-by: Jackson Lee <jackson.lee@chipsnmedia.com>
Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com>
Tested-by: Brandon Brnich <b-brnich@ti.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
drivers/media/platform/chips-media/wave5/wave5-hw.c
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h

index c516d125f55399456ec5cf8ac8c2da7215031c83..2392bce8d840b4053db36db5a4611932dd462f87 100644 (file)
@@ -1763,6 +1763,9 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst)
                        (p_param->skip_intra_trans << 25) |
                        (p_param->strong_intra_smooth_enable << 27) |
                        (p_param->en_still_picture << 30);
+       else if (inst->std == W_AVC_ENC)
+               reg_val |= (p_param->constraint_set1_flag << 29);
+
        vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SPS_PARAM, reg_val);
 
        reg_val = (p_param->lossless_enable) |
index e806973305ce19c2bb31f502bb146db0b1a33950..e6ac7663517802f3081b37005d01395580e5444e 100644 (file)
@@ -918,6 +918,8 @@ static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl)
                case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:
                        inst->enc_param.profile = H264_PROFILE_BP;
                        inst->bit_depth = 8;
+                       if (ctrl->val == V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE)
+                               inst->enc_param.constraint_set1_flag = 1;
                        break;
                case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
                        inst->enc_param.profile = H264_PROFILE_MP;
@@ -1194,6 +1196,7 @@ static int wave5_set_enc_openparam(struct enc_open_param *open_param,
                        open_param->wave_param.intra_period = input.avc_idr_period;
                }
        } else {
+               open_param->wave_param.constraint_set1_flag = input.constraint_set1_flag;
                open_param->wave_param.avc_idr_period = input.avc_idr_period;
        }
        open_param->wave_param.entropy_coding_mode = input.entropy_coding_mode;
@@ -1666,7 +1669,7 @@ static int wave5_vpu_open_enc(struct file *filp)
                          -6, 6, 1, 0);
        v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
                          V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM,
-                         0, 1, 1, 1);
+                         0, 1, 1, 0);
        v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
                          V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION,
                          0, 1, 1, 0);
index dc31689e0d27da0797fe7c93487e68bcee6cca49..7b08fef582171595196617b2440558f1e167a702 100644 (file)
@@ -570,6 +570,7 @@ struct enc_wave_param {
        u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */
        u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
        u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */
+       u32 constraint_set1_flag: 1; /* enable CBP */
        u32 bg_detection: 1; /* enable background detection */
 };