RISC-V: Fix ternary instruction attribute bug

Fix bug of vector.md which generate incorrect information to
VSETVL PASS when testing FMA auto vectorization ternop-3.c.

Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:

	* config/riscv/vector.md: Fix vimuladd instruction bug.

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 15f66efaa4842104d1514cbae60d4200d53c0427..cd696da5d8987e60ed36f24d9e916ded31ca9081 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -388,7 +388,7 @@
             (symbol_ref "INTVAL (operands[7])"))
 
         (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
-                         viwalu,viwmul,vnshift,vimuladd,vaalu,vsmul,vsshift,\
+                         viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
                          vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
                          vfsgnj,vfcmp,vfmuladd,vslideup,vslidedown,vislide1up,\
                          vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\