i386.c (ix86_hard_regno_mode_ok): Always accept all SSE, MMX, 3DNOW modes in SSE...

        * config/i386/i386.c (ix86_hard_regno_mode_ok): Always accept all SSE,
        MMX, 3DNOW modes in SSE registers; always accept all MMX, 3DNOW modes
        in MMX registers.
        * config/i386/i386.h (VALID_SSE2_REG_MODE): Don't include
        VALID_MMX_REG_MODE.
        * config/i386/i386.md (movv4sf_internal, movv4si_internal,
        movv2di_internal, movv2si_internal, movv4hi_internal,
        movv2sf_internal, movv2df_internal, movv8hi_internal,
        movv16qi_internal, movti_internal): Add leading '*' to name.
        (movv2di_internal, movv2df_internal, movv8hi_internal,
        movv16qi_internal, movv2df, movv8hi, movv16qi, movv2di,
        pushv2di, pushv8hi, pushv16qi): Enable for SSE1.
        (movv2si_internal, movv4hi_internal): Add SSE alternatives.
        (movv8qi_internal, movv2sf_internal): Likewise.
        (movtf): Simplify conditional.
        (movv2sf, pushv2sf): Enable for MMX.

From-SVN: r92410

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a84cbe4603d2bad7ad2e414f6aa83d1b2e69c7f5..b9967d64e9b496a715854275533c07b0e68fbf7c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,22 @@
+2004-12-19  Richard Henderson  <rth@redhat.com>
+
+       * config/i386/i386.c (ix86_hard_regno_mode_ok): Always accept all SSE,
+       MMX, 3DNOW modes in SSE registers; always accept all MMX, 3DNOW modes
+       in MMX registers.
+       * config/i386/i386.h (VALID_SSE2_REG_MODE): Don't include
+       VALID_MMX_REG_MODE.
+       * config/i386/i386.md (movv4sf_internal, movv4si_internal, 
+       movv2di_internal, movv2si_internal, movv4hi_internal,
+       movv2sf_internal, movv2df_internal, movv8hi_internal,
+       movv16qi_internal, movti_internal): Add leading '*' to name.
+       (movv2di_internal, movv2df_internal, movv8hi_internal,
+       movv16qi_internal, movv2df, movv8hi, movv16qi, movv2di,
+       pushv2di, pushv8hi, pushv16qi): Enable for SSE1.
+       (movv2si_internal, movv4hi_internal): Add SSE alternatives.
+       (movv8qi_internal, movv2sf_internal): Likewise.
+       (movtf): Simplify conditional.
+       (movv2sf, pushv2sf): Enable for MMX.
+
 2004-12-19  Roger Sayle  <roger@eyesopen.com>
 
        PR middle-end/19068

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index ecd8f073f5fc5db9030d49c0cd218a0f0bb1d474..d1a56d2f524091a7b291abc160ccef56debd0312 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -14927,18 +14927,21 @@ ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
     return VALID_FP_MODE_P (mode);
   if (SSE_REGNO_P (regno))
     {
-      if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
-       return 1;
-      if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
-       return 1;
-      return 0;
+      /* We implement the move patterns for all vector modes into and
+         out of SSE registers, even when no operation instructions
+         are available.  */
+      return (VALID_SSE_REG_MODE (mode)
+             || VALID_SSE2_REG_MODE (mode)
+             || VALID_MMX_REG_MODE (mode)
+             || VALID_MMX_REG_MODE_3DNOW (mode));
     }
   if (MMX_REGNO_P (regno))
     {
-      if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
-       return 1;
-      if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
-       return 1;
+      /* We implement the move patterns for 3DNOW modes even in MMX mode,
+         so if the register is available at all, then we can move data of
+         the given mode into or out of it.  */
+      return (VALID_MMX_REG_MODE (mode)
+             || VALID_MMX_REG_MODE_3DNOW (mode));
     }
   /* We handle both integer and floats in the general purpose registers.
      In future we should be able to handle vector modes as well.  */

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 455a8c3a83bb012b48288abc8ca289fb670926f9..8a912d5f1d1c749bb477ce07d9eca6f591e2feb3 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1063,8 +1063,7 @@ do {                                                                      \
 
 #define VALID_SSE2_REG_MODE(MODE) \
     ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode    \
-     || (MODE) == V2DImode || (MODE) == DFmode                         \
-     || VALID_MMX_REG_MODE (MODE))
+     || (MODE) == V2DImode || (MODE) == DFmode)
 
 #define VALID_SSE_REG_MODE(MODE)                                       \
     ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode      \

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index ffac5cfc94e454f5746a3a80c403e133c466292a..94a2935815244c3a78d470cd7c6b3d3dcd3bf400 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -18431,7 +18431,7 @@
 
 ;; Moves for SSE/MMX regs.
 
-(define_insn "movv4sf_internal"
+(define_insn "*movv4sf_internal"
   [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
        (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
   "TARGET_SSE
@@ -18457,7 +18457,7 @@
   operands[2] = CONST0_RTX (V4SFmode);
 })
 
-(define_insn "movv4si_internal"
+(define_insn "*movv4si_internal"
   [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m")
        (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))]
   "TARGET_SSE
@@ -18498,10 +18498,10 @@
                   (const_string "TI"))]
               (const_string "TI")))])
 
-(define_insn "movv2di_internal"
-  [(set (match_operand:V2DI 0 "nonimmediate_operand" "=Y,Y,m")
-       (match_operand:V2DI 1 "vector_move_operand" "C,Ym,Y"))]
-  "TARGET_SSE2
+(define_insn "*movv2di_internal"
+  [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m")
+       (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))]
+  "TARGET_SSE
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
 {
   switch (which_alternative)
@@ -18553,52 +18553,80 @@
   operands[2] = CONST0_RTX (V2DFmode);
 })
 
-(define_insn "movv8qi_internal"
-  [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m")
-       (match_operand:V8QI 1 "vector_move_operand" "C,ym,y"))]
+(define_insn "*movv2si_internal"
+  [(set (match_operand:V2SI 0 "nonimmediate_operand"
+                                       "=y,y ,m,!y,!*Y,*x,?*x,?m")
+       (match_operand:V2SI 1 "vector_move_operand"
+                                       "C ,ym,y,*Y,y  ,C ,*xm,*x"))]
   "TARGET_MMX
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "@
+    pxor\t%0, %0
+    movq\t{%1, %0|%0, %1}
+    movq\t{%1, %0|%0, %1}
+    movdq2q\t{%1, %0|%0, %1}
+    movq2dq\t{%1, %0|%0, %1}
     pxor\t%0, %0
     movq\t{%1, %0|%0, %1}
     movq\t{%1, %0|%0, %1}"
-  [(set_attr "type" "mmxmov")
+  [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov")
    (set_attr "mode" "DI")])
 
-(define_insn "movv4hi_internal"
-  [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m")
-       (match_operand:V4HI 1 "vector_move_operand" "C,ym,y"))]
+(define_insn "*movv4hi_internal"
+  [(set (match_operand:V4HI 0 "nonimmediate_operand"
+                                       "=y,y ,m,!y,!*Y,*x,?*x,?m")
+       (match_operand:V4HI 1 "vector_move_operand"
+                                       "C ,ym,y,*Y,y  ,C ,*xm,*x"))]
   "TARGET_MMX
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "@
+    pxor\t%0, %0
+    movq\t{%1, %0|%0, %1}
+    movq\t{%1, %0|%0, %1}
+    movdq2q\t{%1, %0|%0, %1}
+    movq2dq\t{%1, %0|%0, %1}
     pxor\t%0, %0
     movq\t{%1, %0|%0, %1}
     movq\t{%1, %0|%0, %1}"
-  [(set_attr "type" "mmxmov")
+  [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov")
    (set_attr "mode" "DI")])
 
-(define_insn "movv2si_internal"
-  [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m")
-       (match_operand:V2SI 1 "vector_move_operand" "C,ym,y"))]
+(define_insn "*movv8qi_internal"
+  [(set (match_operand:V8QI 0 "nonimmediate_operand"
+                                       "=y,y ,m,!y,!*Y,*x,?*x,?m")
+       (match_operand:V8QI 1 "vector_move_operand"
+                                       "C ,ym,y,*Y,y  ,C ,*xm,*x"))]
   "TARGET_MMX
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "@
+    pxor\t%0, %0
+    movq\t{%1, %0|%0, %1}
+    movq\t{%1, %0|%0, %1}
+    movdq2q\t{%1, %0|%0, %1}
+    movq2dq\t{%1, %0|%0, %1}
     pxor\t%0, %0
     movq\t{%1, %0|%0, %1}
     movq\t{%1, %0|%0, %1}"
-  [(set_attr "type" "mmxcvt")
+  [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov")
    (set_attr "mode" "DI")])
 
-(define_insn "movv2sf_internal"
-  [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m")
-        (match_operand:V2SF 1 "vector_move_operand" "C,ym,y"))]
-  "TARGET_3DNOW
+(define_insn "*movv2sf_internal"
+  [(set (match_operand:V2SF 0 "nonimmediate_operand"
+                                       "=y,y ,m,!y,!*Y,*x,?*x,?m")
+        (match_operand:V2SF 1 "vector_move_operand"
+                                       "C ,ym,y,*Y,y  ,C ,*xm,*x"))]
+  "TARGET_MMX
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "@
     pxor\t%0, %0
     movq\t{%1, %0|%0, %1}
+    movq\t{%1, %0|%0, %1}
+    movdq2q\t{%1, %0|%0, %1}
+    movq2dq\t{%1, %0|%0, %1}
+    xorps\t%0, %0
+    movq\t{%1, %0|%0, %1}
     movq\t{%1, %0|%0, %1}"
-  [(set_attr "type" "mmxcvt")
+  [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov")
    (set_attr "mode" "DI")])
 
 (define_expand "movti"
@@ -18618,17 +18646,14 @@
        (match_operand:TF 1 "nonimmediate_operand" ""))]
   "TARGET_64BIT"
 {
-  if (TARGET_64BIT)
-    ix86_expand_move (TFmode, operands);
-  else
-    ix86_expand_vector_move (TFmode, operands);
+  ix86_expand_move (TFmode, operands);
   DONE;
 })
 
-(define_insn "movv2df_internal"
+(define_insn "*movv2df_internal"
   [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
        (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
-  "TARGET_SSE2
+  "TARGET_SSE
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
 {
   switch (which_alternative)
@@ -18650,7 +18675,9 @@
 }
   [(set_attr "type" "ssemov")
    (set (attr "mode")
-        (cond [(eq_attr "alternative" "0,1")
+        (cond [(eq (symbol_ref "TARGET_SSE2") (const_int 0))
+                (const_string "V4SF")
+              (eq_attr "alternative" "0,1")
                 (if_then_else
                   (ne (symbol_ref "optimize_size")
                       (const_int 0))
@@ -18666,10 +18693,10 @@
                   (const_string "V2DF"))]
               (const_string "V2DF")))])
 
-(define_insn "movv8hi_internal"
+(define_insn "*movv8hi_internal"
   [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m")
        (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))]
-  "TARGET_SSE2
+  "TARGET_SSE
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
 {
   switch (which_alternative)
@@ -18707,10 +18734,10 @@
                   (const_string "TI"))]
               (const_string "TI")))])
 
-(define_insn "movv16qi_internal"
+(define_insn "*movv16qi_internal"
   [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
        (match_operand:V16QI 1 "vector_move_operand" "C,xm,x"))]
-  "TARGET_SSE2
+  "TARGET_SSE
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
 {
   switch (which_alternative)
@@ -18751,7 +18778,7 @@
 (define_expand "movv2df"
   [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
        (match_operand:V2DF 1 "nonimmediate_operand" ""))]
-  "TARGET_SSE2"
+  "TARGET_SSE"
 {
   ix86_expand_vector_move (V2DFmode, operands);
   DONE;
@@ -18760,7 +18787,7 @@
 (define_expand "movv8hi"
   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
        (match_operand:V8HI 1 "nonimmediate_operand" ""))]
-  "TARGET_SSE2"
+  "TARGET_SSE"
 {
   ix86_expand_vector_move (V8HImode, operands);
   DONE;
@@ -18769,7 +18796,7 @@
 (define_expand "movv16qi"
   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
        (match_operand:V16QI 1 "nonimmediate_operand" ""))]
-  "TARGET_SSE2"
+  "TARGET_SSE"
 {
   ix86_expand_vector_move (V16QImode, operands);
   DONE;
@@ -18796,7 +18823,7 @@
 (define_expand "movv2di"
   [(set (match_operand:V2DI 0 "nonimmediate_operand" "")
        (match_operand:V2DI 1 "nonimmediate_operand" ""))]
-  "TARGET_SSE2"
+  "TARGET_SSE"
 {
   ix86_expand_vector_move (V2DImode, operands);
   DONE;
@@ -18832,7 +18859,7 @@
 (define_expand "movv2sf"
   [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
        (match_operand:V2SF 1 "nonimmediate_operand" ""))]
-   "TARGET_3DNOW"
+  "TARGET_MMX"
 {
   ix86_expand_vector_move (V2SFmode, operands);
   DONE;
@@ -18853,19 +18880,19 @@
 (define_insn "*pushv2di"
   [(set (match_operand:V2DI 0 "push_operand" "=<")
        (match_operand:V2DI 1 "register_operand" "x"))]
-  "TARGET_SSE2"
+  "TARGET_SSE"
   "#")
 
 (define_insn "*pushv8hi"
   [(set (match_operand:V8HI 0 "push_operand" "=<")
        (match_operand:V8HI 1 "register_operand" "x"))]
-  "TARGET_SSE2"
+  "TARGET_SSE"
   "#")
 
 (define_insn "*pushv16qi"
   [(set (match_operand:V16QI 0 "push_operand" "=<")
        (match_operand:V16QI 1 "register_operand" "x"))]
-  "TARGET_SSE2"
+  "TARGET_SSE"
   "#")
 
 (define_insn "*pushv4sf"
@@ -18901,7 +18928,7 @@
 (define_insn "*pushv2sf"
   [(set (match_operand:V2SF 0 "push_operand" "=<")
        (match_operand:V2SF 1 "register_operand" "y"))]
-  "TARGET_3DNOW"
+  "TARGET_MMX"
   "#")
 
 (define_split
@@ -18927,7 +18954,7 @@
    operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
 
 
-(define_insn "movti_internal"
+(define_insn "*movti_internal"
   [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
        (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
   "TARGET_SSE && !TARGET_64BIT