#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-
/* Board Clock */
#define CFG_EXTRA_ENV_SETTINGS \
/* Environment compatibility */
-/* SH Ether */
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-
/* Board Clock */
#define CFG_EXTRA_ENV_SETTINGS \
#define CFG_SYS_SDRAM_BASE 0x20000000
#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
-/* Network interface */
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-
#endif /* __GRPEACH_H */
#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-
/* Board Clock */
#define CFG_EXTRA_ENV_SETTINGS \
#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-
/* Board Clock */
#define CFG_EXTRA_ENV_SETTINGS \
#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-
/* Board Clock */
#define CFG_EXTRA_ENV_SETTINGS \
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-
/* Board Clock */
#define CFG_EXTRA_ENV_SETTINGS \
/* SCIF */
#define CFG_SCIF_A
-/* SH Ether */
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-
/* Board Clock */
#define CFG_EXTRA_ENV_SETTINGS \
/* Environment compatibility */
-/* SH Ether */
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID
-
/* Board Clock */
/* XTAL_CLK : 33.33MHz */