arm: [MVE intrinsics] remove v[id]dup expanders

We use code_for_mve_q_u_insn, rather than the expanders used by the
previous implementation, so we can remove the expanders and their
declaration as builtins.

2024-08-21  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/arm/arm_mve_builtins.def (vddupq_n_u, vidupq_n_u)
	(vddupq_m_n_u, vidupq_m_n_u): Delete.
	* config/arm/mve.md (mve_vidupq_n_u<mode>, mve_vidupq_m_n_u<mode>)
	(mve_vddupq_n_u<mode>, mve_vddupq_m_n_u<mode>): Delete.

diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def
index dd99a90b95219a0c475775dd433cc5413f2f6fce..13070d958fcc52ef9aaa003fb0b1964d7e89ed7a 100644 (file)
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -803,10 +803,6 @@ VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, viwdupq_m_wb_u, v16qi, v8hi, v4si
 VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, vdwdupq_m_wb_u, v16qi, v8hi, v4si)
 VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, viwdupq_m_n_u, v16qi, v8hi, v4si)
 VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, vdwdupq_m_n_u, v16qi, v8hi, v4si)
-VAR3 (BINOP_UNONE_UNONE_IMM, vddupq_n_u, v16qi, v8hi, v4si)
-VAR3 (BINOP_UNONE_UNONE_IMM, vidupq_n_u, v16qi, v8hi, v4si)
-VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vddupq_m_n_u, v16qi, v8hi, v4si)
-VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vidupq_m_n_u, v16qi, v8hi, v4si)
 VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_n_u, v16qi, v4si, v8hi)
 VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_n_u, v16qi, v4si, v8hi)
 VAR1 (STRSBWBU, vstrwq_scatter_base_wb_u, v4si)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index d6022276240e2b681b54331612e5856641f64317..ffb4a10fd226169822656ccd324af389f1cd3205 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -5061,22 +5061,6 @@
   (set_attr "length" "4")])
 
 ;;
-;; [vidupq_n_u])
-;;
-(define_expand "mve_vidupq_n_u<mode>"
- [(match_operand:MVE_2 0 "s_register_operand")
-  (match_operand:SI 1 "s_register_operand")
-  (match_operand:SI 2 "mve_imm_selective_upto_8")]
- "TARGET_HAVE_MVE"
-{
-  rtx temp = gen_reg_rtx (SImode);
-  emit_move_insn (temp, operands[1]);
-  rtx inc = gen_int_mode (INTVAL(operands[2]) * <MVE_LANES>, SImode);
-  emit_insn (gen_mve_vidupq_u<mode>_insn (operands[0], temp, operands[1],
-                                         operands[2], inc));
-  DONE;
-})
-
 ;;
 ;; [vddupq_u_insn, vidupq_u_insn]
 ;;
@@ -5091,26 +5075,6 @@
  "TARGET_HAVE_MVE"
  "<mve_insn>.u%#<V_sz_elem>\t%q0, %1, %3")
 
-;;
-;; [vidupq_m_n_u])
-;;
-(define_expand "mve_vidupq_m_n_u<mode>"
-  [(match_operand:MVE_2 0 "s_register_operand")
-   (match_operand:MVE_2 1 "s_register_operand")
-   (match_operand:SI 2 "s_register_operand")
-   (match_operand:SI 3 "mve_imm_selective_upto_8")
-   (match_operand:<MVE_VPRED> 4 "vpr_register_operand")]
-  "TARGET_HAVE_MVE"
-{
-  rtx temp = gen_reg_rtx (SImode);
-  emit_move_insn (temp, operands[2]);
-  rtx inc = gen_int_mode (INTVAL(operands[3]) * <MVE_LANES>, SImode);
-  emit_insn (gen_mve_vidupq_m_wb_u<mode>_insn(operands[0], operands[1], temp,
-                                            operands[2], operands[3],
-                                            operands[4], inc));
-  DONE;
-})
-
 ;;
 ;; [vddupq_m_wb_u_insn, vidupq_m_wb_u_insn]
 ;;
@@ -5129,43 +5093,6 @@
  [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_u<mode>_insn"))
   (set_attr "length""8")])
 
-;;
-;; [vddupq_n_u])
-;;
-(define_expand "mve_vddupq_n_u<mode>"
- [(match_operand:MVE_2 0 "s_register_operand")
-  (match_operand:SI 1 "s_register_operand")
-  (match_operand:SI 2 "mve_imm_selective_upto_8")]
- "TARGET_HAVE_MVE"
-{
-  rtx temp = gen_reg_rtx (SImode);
-  emit_move_insn (temp, operands[1]);
-  rtx inc = gen_int_mode (INTVAL(operands[2]) * <MVE_LANES>, SImode);
-  emit_insn (gen_mve_vddupq_u<mode>_insn (operands[0], temp, operands[1],
-                                         operands[2], inc));
-  DONE;
-})
-
-;;
-;; [vddupq_m_n_u])
-;;
-(define_expand "mve_vddupq_m_n_u<mode>"
-  [(match_operand:MVE_2 0 "s_register_operand")
-   (match_operand:MVE_2 1 "s_register_operand")
-   (match_operand:SI 2 "s_register_operand")
-   (match_operand:SI 3 "mve_imm_selective_upto_8")
-   (match_operand:<MVE_VPRED> 4 "vpr_register_operand")]
-  "TARGET_HAVE_MVE"
-{
-  rtx temp = gen_reg_rtx (SImode);
-  emit_move_insn (temp, operands[2]);
-  rtx inc = gen_int_mode (INTVAL(operands[3]) * <MVE_LANES>, SImode);
-  emit_insn (gen_mve_vddupq_m_wb_u<mode>_insn(operands[0], operands[1], temp,
-                                            operands[2], operands[3],
-                                            operands[4], inc));
-  DONE;
-})
-
 ;;
 ;; [vdwdupq_n_u])
 ;;