clk: renesas: rzg2l: Select correct div round macro

Variable foutvco_rate is an unsigned long, not an unsigned long long.

Cc: stable@kernel.org
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Closes: https://lore.kernel.org/CAMuHMdVf7dSeqAhtyxDCFuCheQRzwS-8996Rr2Ntui21uiBgdA@mail.gmail.com
Fixes: dabf72b85f29 ("clk: renesas: rzg2l: Fix FOUTPOSTDIV clk")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251114194529.3304361-1-chris.brandt@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index dfe0f5e87d8cfa8a0f5a620f07ec59df533abd1d..0bcf64b152e0780da359b081608401b5f39497ac 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -572,8 +572,8 @@ rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params,
        foutvco_rate = div_u64(mul_u32_u32(EXTAL_FREQ_IN_MEGA_HZ * MEGA,
                                           (params->pl5_intin << 24) + params->pl5_fracin),
                               params->pl5_refdiv) >> 24;
-       foutpostdiv_rate = DIV_ROUND_CLOSEST_ULL(foutvco_rate,
-                                                params->pl5_postdiv1 * params->pl5_postdiv2);
+       foutpostdiv_rate = DIV_ROUND_CLOSEST(foutvco_rate,
+                                            params->pl5_postdiv1 * params->pl5_postdiv2);
 
        return foutpostdiv_rate;
 }