OptionalClk, //
},
device::{
- Bound,
Core,
Device, //
},
- devres::Devres,
dma::{
Device as DmaDevice,
DmaMask, //
sizes::SZ_2M,
sync::{
aref::ARef,
- Arc,
Mutex, //
},
time, //
regs::gpu_control::*, //
};
-pub(crate) type IoMem = kernel::io::mem::IoMem<'static, SZ_2M>;
+pub(crate) type IoMem<'a> = kernel::io::mem::IoMem<'a, SZ_2M>;
pub(crate) struct TyrDrmDriver;
pub(crate) gpu_info: GpuInfo,
}
-fn issue_soft_reset(dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result {
- let io = (*iomem).access(dev)?;
- io.write_reg(GPU_COMMAND::reset(ResetMode::SoftReset));
+fn issue_soft_reset(dev: &Device, iomem: &IoMem<'_>) -> Result {
+ iomem.write_reg(GPU_COMMAND::reset(ResetMode::SoftReset));
poll::read_poll_timeout(
- || {
- let io = (*iomem).access(dev)?;
- Ok(io.read(GPU_IRQ_RAWSTAT))
- },
+ || Ok(iomem.read(GPU_IRQ_RAWSTAT)),
|status| status.reset_completed(),
time::Delta::from_millis(1),
time::Delta::from_millis(100),
let sram_regulator = Regulator::<regulator::Enabled>::get(pdev.as_ref(), c"sram")?;
let request = pdev.io_request_by_index(0).ok_or(ENODEV)?;
- let iomem = Arc::new(request.iomap_sized::<SZ_2M>()?.into_devres()?, GFP_KERNEL)?;
+ let iomem = request.iomap_sized::<SZ_2M>()?;
issue_soft_reset(pdev.as_ref(), &iomem)?;
gpu::l2_power_on(pdev.as_ref(), &iomem)?;
- let gpu_info = GpuInfo::new(pdev.as_ref(), &iomem)?;
+ let gpu_info = GpuInfo::new(&iomem);
gpu_info.log(pdev.as_ref());
let pa_bits = MMU_FEATURES::from_raw(gpu_info.mmu_features)
Bound,
Device, //
},
- devres::Devres,
io::{
poll,
register::Array,
pub(crate) struct GpuInfo(pub(crate) uapi::drm_panthor_gpu_info);
impl GpuInfo {
- pub(crate) fn new(dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result<Self> {
- let io = (*iomem).access(dev)?;
-
- Ok(Self(uapi::drm_panthor_gpu_info {
+ pub(crate) fn new(io: &IoMem<'_>) -> Self {
+ Self(uapi::drm_panthor_gpu_info {
gpu_id: io.read(GPU_ID).into_raw(),
gpu_rev: io.read(REVIDR).into_raw(),
csf_id: io.read(CSF_ID).into_raw(),
pad: 0,
//GPU_FEATURES register is not available; it was introduced in arch 11.x.
gpu_features: 0,
- }))
+ })
}
pub(crate) fn log(&self, dev: &Device<Bound>) {
}];
/// Powers on the l2 block.
-pub(crate) fn l2_power_on(dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result {
- let io = (*iomem).access(dev)?;
+pub(crate) fn l2_power_on(dev: &Device, io: &IoMem<'_>) -> Result {
io.write_reg(L2_PWRON_LO::zeroed().with_const_request::<1>());
poll::read_poll_timeout(
- || {
- let io = (*iomem).access(dev)?;
- Ok(io.read(L2_READY_LO))
- },
+ || Ok(io.read(L2_READY_LO)),
|status| status.ready() == 1,
Delta::from_millis(1),
Delta::from_millis(100),