; Test Data Class (TDC)
UNSPEC_TDC_INSN
+ UNSPEC_SIGNBIT
; Byte-wise Population Count
UNSPEC_POPCNT
S390_TDC_INFINITY
S390_TDC_NORMAL_BFP])
-(define_int_attr tdc_insn [(S390_TDC_SIGNBIT_SET "signbit")
+(define_int_attr tdc_insn [(S390_TDC_SIGNBIT_SET "signbit_tdc")
(S390_TDC_FINITE "isfinite")
(S390_TDC_INFINITY "isinf")
(S390_TDC_NORMAL_BFP "isnormal")
(unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
"TARGET_HARD_DFP")
+(define_mode_iterator SIGNBIT_SINGLE [(SF "TARGET_HARD_FLOAT")
+ (SD "TARGET_HARD_DFP")])
+(define_expand "signbit<mode>2"
+ [(match_operand:SI 0 "register_operand")
+ (match_operand:SIGNBIT_SINGLE 1 "nonimmediate_operand")]
+ ""
+{
+ if (TARGET_VX && TARGET_64BIT)
+ {
+ emit_insn (gen_rtx_SET (operands[0], simplify_gen_subreg (SImode, operands[1], <MODE>mode, 0)));
+ emit_insn (gen_rtx_SET (operands[0], gen_rtx_LSHIFTRT (SImode, operands[0], GEN_INT (31))));
+ }
+ else if (TARGET_Z10 && TARGET_64BIT)
+ emit_insn (gen_signbit<mode>2_z10 (operands[0], operands[1]));
+ else
+ emit_insn (gen_signbit_tdc<mode>2 (operands[0], force_reg (<MODE>mode, operands[1])));
+ DONE;
+})
+
+(define_insn "signbit<mode>2_z10"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:SIGNBIT_SINGLE 1 "nonimmediate_operand" "fRT")]
+ UNSPEC_SIGNBIT))]
+ "TARGET_Z10 && TARGET_64BIT"
+ "#")
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand")
+ (unspec:SI [(match_operand:SIGNBIT_SINGLE 1 "register_operand")]
+ UNSPEC_SIGNBIT))]
+ "TARGET_Z10 && TARGET_64BIT && reload_completed"
+ [(set (match_dup 0) (match_dup 1))
+ (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 63)))]
+{
+ operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
+ operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));
+})
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand")
+ (unspec:SI [(match_operand:SIGNBIT_SINGLE 1 "memory_operand")]
+ UNSPEC_SIGNBIT))]
+ "TARGET_Z10 && TARGET_64BIT && reload_completed"
+ [(set (match_dup 0) (match_dup 1))
+ (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 31)))]
+{
+ operands[1] = change_address (operands[1], SImode, 0);
+})
+
+(define_mode_iterator SIGNBIT_DBL_TETRA [(DF "TARGET_HARD_FLOAT")
+ (TF "TARGET_HARD_FLOAT")
+ (DD "TARGET_HARD_DFP")
+ (TD "TARGET_HARD_DFP")])
+(define_expand "signbit<mode>2"
+ [(match_operand:SI 0 "register_operand")
+ (match_operand:SIGNBIT_DBL_TETRA 1 "nonimmediate_operand")]
+ ""
+{
+ if (TARGET_Z10 && TARGET_64BIT)
+ {
+ rtx reg_di = gen_reg_rtx (DImode);
+ if (<MODE>mode == TFmode || <MODE>mode == TDmode)
+ {
+ rtx reg_ti = gen_reg_rtx (TImode);
+ emit_insn (gen_rtx_SET (reg_ti, simplify_gen_subreg (TImode, operands[1], <MODE>mode, 0)));
+ emit_insn (gen_rtx_SET (reg_di, simplify_gen_subreg (DImode, reg_ti, TImode, 0)));
+ }
+ else
+ emit_insn (gen_rtx_SET (reg_di, simplify_gen_subreg (DImode, operands[1], <MODE>mode, 0)));
+ emit_insn (gen_rtx_SET (reg_di, gen_rtx_LSHIFTRT (DImode, reg_di, GEN_INT (63))));
+ rtx subreg = gen_rtx_SUBREG (SImode, reg_di, 4);
+ SUBREG_PROMOTED_VAR_P (subreg) = 1;
+ SUBREG_PROMOTED_SET (subreg, SRP_SIGNED_AND_UNSIGNED);
+ emit_insn (gen_rtx_SET (operands[0], subreg));
+ }
+ else
+ emit_insn (gen_signbit_tdc<mode>2 (operands[0], force_reg (<MODE>mode, operands[1])));
+ DONE;
+})
+
; This extracts CC into a GPR properly shifted. The actual IPM
; instruction will be issued by reload. The constraint of operand 1
; forces reload to use a GPR. So reload will issue a movcc insn for
#include "isfinite-isinf-isnormal-signbit.h"
-/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 1 } } SIGNBIT long double */
-/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 } } SIGNBIT _Decimal128 */
+/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 0 { target lp64 } } } SIGNBIT long double */
+/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 0 { target lp64 } } } SIGNBIT _Decimal128 */
+/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } SIGNBIT long double */
+/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } SIGNBIT _Decimal128 */
/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,4032} 1 } } ISFINITE long double */
/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,4032} 1 } } ISFINITE _Decimal128 */
/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,48} 1 } } ISINF long double */
#include "isfinite-isinf-isnormal-signbit.h"
-/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 1 } } */
-/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 } } */
+/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 0 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 0 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 1 { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } */
/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,4032} 1 } } */
/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,4032} 1 } } */
/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,48} 1 } } */
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2 -march=z900 -save-temps" } */
+/* { dg-final { scan-assembler-times {\ttceb\t} 2 } } */
+/* { dg-final { scan-assembler-times {\ttcdb\t} 2 } } */
+/* { dg-final { scan-assembler-times {\ttcxb\t} 2 } } */
+
+/* Binary Floating-Point */
+
+__attribute__ ((noipa))
+int signbit_float_reg (float x) { return __builtin_signbit (x); }
+__attribute__ ((noipa))
+int signbit_float_mem (float *x) { return __builtin_signbit (*x); }
+__attribute__ ((noipa))
+int signbit_double_reg (double x) { return __builtin_signbit (x); }
+__attribute__ ((noipa))
+int signbit_double_mem (double *x) { return __builtin_signbit (*x); }
+
+__attribute__ ((noipa))
+int
+signbit_longdouble_reg (long double x)
+{
+ __asm__ ("" : "+f" (x));
+ return __builtin_signbit (x);
+}
+
+__attribute__ ((noipa))
+int signbit_longdouble_mem (long double *x) { return __builtin_signbit (*x); }
+
+#include "signbit.h"
+TEST (float, float, __builtin_inff(), __builtin_nanf("42"), 0.f, 42.f)
+TEST (double, double, __builtin_inf(), __builtin_nan("42"), 0., 42.)
+TEST (longdouble, long double, __builtin_infl(), __builtin_nanl("42"), 0.L, 42.L)
+
+int
+main (void)
+{
+ test_float ();
+ test_double ();
+ test_longdouble ();
+}
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2 -march=z9-ec -mzarch -save-temps" } */
+/* { dg-final { scan-assembler-times {\ttdcet\t} 2 } } */
+/* { dg-final { scan-assembler-times {\ttdcdt\t} 2 } } */
+/* { dg-final { scan-assembler-times {\ttdcxt\t} 2 } } */
+
+/* Decimal Floating-Point */
+
+__attribute__ ((noipa))
+int signbit_dec32_reg (_Decimal32 x) { return __builtin_signbit (x); }
+__attribute__ ((noipa))
+int signbit_dec32_mem (_Decimal32 *x) { return __builtin_signbit (*x); }
+__attribute__ ((noipa))
+int signbit_dec64_reg (_Decimal64 x) { return __builtin_signbit (x); }
+__attribute__ ((noipa))
+int signbit_dec64_mem (_Decimal64 *x) { return __builtin_signbit (*x); }
+
+__attribute__ ((noipa))
+int
+signbit_dec128_reg (_Decimal128 x)
+{
+ __asm__ ("" : "+f" (x));
+ return __builtin_signbit (x);
+}
+
+__attribute__ ((noipa))
+int signbit_dec128_mem (_Decimal128 *x) { return __builtin_signbit (*x); }
+
+#include "signbit.h"
+TEST (dec32, _Decimal32, __builtin_infd32(), __builtin_nand32("42"), 0.df, 42.df)
+TEST (dec64, _Decimal64, __builtin_infd64(), __builtin_nand64("42"), 0.dd, 42.dd)
+TEST (dec128, _Decimal128, __builtin_infd128(), __builtin_nand128("42"), 0.dl, 42.dl)
+
+int
+main (void)
+{
+ test_dec32 ();
+ test_dec64 ();
+ test_dec128 ();
+}
--- /dev/null
+/* { dg-do run { target lp64 } } */
+/* { dg-options "-O2 -march=z10 -save-temps" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/* Binary Floating-Point */
+
+/*
+** signbit_float_reg:
+** lgdr (%r[0-9]+),%f0
+** srlg (%r[0-9]+),\1,63
+** lgfr %r2,\2
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_float_reg (float x) { return __builtin_signbit (x); }
+
+/*
+** signbit_float_mem:
+** l (%r[0-9]+),0\(%r2\)
+** srl \1,31
+** lgfr %r2,\1
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_float_mem (float *x) { return __builtin_signbit (*x); }
+
+/*
+** signbit_double_reg:
+** lgdr (%r[0-9]+),%f0
+** srlg %r2,\1,63
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_double_reg (double x) { return __builtin_signbit (x); }
+
+/*
+** signbit_double_mem:
+** lg (%r[0-9]+),0\(%r2\)
+** srlg %r2,\1,63
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_double_mem (double *x) { return __builtin_signbit (*x); }
+
+/*
+** signbit_longdouble_reg:
+** ld %f0,0\(%r2\)
+** ld %f2,8\(%r2\)
+** lgdr (%r[0-9]+),%f0
+** srlg %r2,\1,63
+** br %r14
+*/
+__attribute__ ((noipa))
+int
+signbit_longdouble_reg (long double x)
+{
+ __asm__ ("" : "+f" (x));
+ return __builtin_signbit (x);
+}
+
+/*
+** signbit_longdouble_mem:
+** lg (%r[0-9]+),0\(%r2\)
+** srlg %r2,\1,63
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_longdouble_mem (long double *x) { return __builtin_signbit (*x); }
+
+/* Decimal Floating-Point */
+
+/*
+** signbit_dec32_reg:
+** lgdr (%r[0-9]+),%f0
+** srlg (%r[0-9]+),\1,63
+** lgfr %r2,\2
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_dec32_reg (_Decimal32 x) { return __builtin_signbit (x); }
+
+/*
+** signbit_dec32_mem:
+** l (%r[0-9]+),0\(%r2\)
+** srl \1,31
+** lgfr %r2,\1
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_dec32_mem (_Decimal32 *x) { return __builtin_signbit (*x); }
+
+/*
+** signbit_dec64_reg:
+** lgdr (%r[0-9]+),%f0
+** srlg %r2,\1,63
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_dec64_reg (_Decimal64 x) { return __builtin_signbit (x); }
+
+/*
+** signbit_dec64_mem:
+** lg (%r[0-9]+),0\(%r2\)
+** srlg %r2,\1,63
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_dec64_mem (_Decimal64 *x) { return __builtin_signbit (*x); }
+
+/*
+** signbit_dec128_reg:
+** ld %f0,0\(%r2\)
+** ld %f2,8\(%r2\)
+** lgdr (%r[0-9]+),%f0
+** srlg %r2,\1,63
+** br %r14
+*/
+__attribute__ ((noipa))
+int
+signbit_dec128_reg (_Decimal128 x)
+{
+ __asm__ ("" : "+f" (x));
+ return __builtin_signbit (x);
+}
+
+/*
+** signbit_dec128_mem:
+** lg (%r[0-9]+),0\(%r2\)
+** srlg %r2,\1,63
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_dec128_mem (_Decimal128 *x) { return __builtin_signbit (*x); }
+
+#include "signbit.h"
+TEST (float, float, __builtin_inff(), __builtin_nanf("42"), 0.f, 42.f)
+TEST (double, double, __builtin_inf(), __builtin_nan("42"), 0., 42.)
+TEST (longdouble, long double, __builtin_infl(), __builtin_nanl("42"), 0.L, 42.L)
+TEST (dec32, _Decimal32, __builtin_infd32(), __builtin_nand32("42"), 0.df, 42.df)
+TEST (dec64, _Decimal64, __builtin_infd64(), __builtin_nand64("42"), 0.dd, 42.dd)
+TEST (dec128, _Decimal128, __builtin_infd128(), __builtin_nand128("42"), 0.dl, 42.dl)
+
+int
+main (void)
+{
+ test_float ();
+ test_double ();
+ test_longdouble ();
+ test_dec32 ();
+ test_dec64 ();
+ test_dec128 ();
+}
--- /dev/null
+/* { dg-do run { target lp64 } } */
+/* { dg-require-effective-target s390_vx } */
+/* { dg-options "-O2 -march=z13 -save-temps" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/* Binary Floating-Point */
+
+/*
+** signbit_float_reg:
+** vlgvf (%r[0-9]+),%v0,0
+** risbgn %r2,\1,64-1,128\+63,32\+1
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_float_reg (float x) { return __builtin_signbit (x); }
+
+/*
+** signbit_float_mem:
+** l (%r[0-9]+),0\(%r2\)
+** risbgn %r2,\1,64-1,128\+63,32\+1
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_float_mem (float *x) { return __builtin_signbit (*x); }
+
+/* Decimal Floating-Point */
+
+/*
+** signbit_dec32_reg:
+** vlgvf (%r[0-9]+),%v0,0
+** risbgn %r2,\1,64-1,128\+63,32\+1
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_dec32_reg (_Decimal32 x) { return __builtin_signbit (x); }
+
+/*
+** signbit_dec32_mem:
+** l (%r[0-9]+),0\(%r2\)
+** risbgn %r2,\1,64-1,128\+63,32\+1
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_dec32_mem (_Decimal32 *x) { return __builtin_signbit (*x); }
+
+#include "signbit.h"
+TEST (float, float, __builtin_inff(), __builtin_nanf("42"), 0.f, 42.f)
+TEST (dec32, _Decimal32, __builtin_infd32(), __builtin_nand32("42"), 0.df, 42.df)
+
+int
+main (void)
+{
+ test_float ();
+ test_dec32 ();
+}
--- /dev/null
+/* { dg-do run { target lp64 } } */
+/* { dg-options "-O2 -march=z14 -save-temps" } */
+
+/*
+** signbit_longdouble_reg:
+** ld %f0,0(%r2);ld %f2,8+0(%r2)
+** lgdr (%r[0-9]+),%f0
+** srlg %r2,\1,63
+** br %r14
+*/
+__attribute__ ((noipa))
+int
+signbit_longdouble_reg (long double x)
+{
+ __asm__ ("" : "+f" (x));
+ return __builtin_signbit (x);
+}
+
+/*
+** signbit_longdouble_mem:
+** lg (%r[0-9]+),0\(%r2\)
+** srlg %r2,\1,63
+** br %r14
+*/
+__attribute__ ((noipa))
+int signbit_longdouble_mem (long double *x) { return __builtin_signbit (*x); }
+
+#include "signbit.h"
+TEST (longdouble, long double, __builtin_infl(), __builtin_nanl("42"), 0.L, 42.L)
+
+int
+main (void)
+{
+ test_longdouble ();
+}
--- /dev/null
+#define TEST(T, U, I, N, C0, C42) \
+ void test_##T (void) \
+ { \
+ U tmp; \
+ int x; \
+ \
+ x = signbit_##T##_reg(C42); \
+ x += signbit_##T##_reg(C0); \
+ x += signbit_##T##_reg(I); \
+ x += signbit_##T##_reg(N); \
+ tmp = C42; \
+ x += signbit_##T##_mem(&tmp); \
+ tmp = C0; \
+ x += signbit_##T##_mem(&tmp); \
+ tmp = I; \
+ x += signbit_##T##_mem(&tmp); \
+ tmp = N; \
+ x += signbit_##T##_mem(&tmp); \
+ if (x != 0) \
+ __builtin_abort(); \
+ \
+ x = signbit_##T##_reg(-C42); \
+ x += signbit_##T##_reg(-C0); \
+ x += signbit_##T##_reg(-I); \
+ x += signbit_##T##_reg(-N); \
+ tmp = -C42; \
+ x += signbit_##T##_mem(&tmp); \
+ tmp = -C0; \
+ x += signbit_##T##_mem(&tmp); \
+ tmp = -I; \
+ x += signbit_##T##_mem(&tmp); \
+ tmp = -N; \
+ x += signbit_##T##_mem(&tmp); \
+ if (x != 8) \
+ __builtin_abort(); \
+ }
projects / thirdparty / gcc.git / commitdiff
