]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
ARM: dts: stm32: add stm32mp157f-dk2 board support
authorAmelie Delaunay <amelie.delaunay@foss.st.com>
Tue, 3 Jun 2025 09:02:13 +0000 (11:02 +0200)
committerAlexandre Torgue <alexandre.torgue@foss.st.com>
Fri, 4 Jul 2025 09:24:12 +0000 (11:24 +0200)
STM32MP157F-DK2 board embeds a STM32MP157F SoC. This SoC contains the same
level of feature than a STM32MP157C SOC but A7 clock frequency can reach
800MHz, hence the inclusion of the newly introduced stm32mp15xf.dtsi.

As for other latest STM32 MPU families, STM32MP157F-DK2 relies on OP-TEE
SCMI services for SoC clock and reset controllers resources, and for PMIC,
now under OP-TEE control. That's why stm32mp157f-dk2-scmi.dtsi is
introduced, to move all clocks, resets and regulators to SCMI-based ones.

To "disable" SCMI, just need to comment stm32mp157f-dk2-scmi.dtsi inclusion
and to replace &scmi_v3v3 with &v3v3, then to disable arm_wdt and to enable
i2c4 and its subnodes for PMIC support by Linux. Reconfigure usbotg for
dual role with type-C support if needed.

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-7-5be0854a9299@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
arch/arm/boot/dts/st/Makefile
arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi [new file with mode: 0644]
arch/arm/boot/dts/st/stm32mp157f-dk2.dts [new file with mode: 0644]

index cc9948b9870f7f73629573149bfd342af75b07da..66d4f96da5ddbba337c2f290512a74b85e5c568e 100644 (file)
@@ -72,7 +72,8 @@ dtb-$(CONFIG_ARCH_STM32) += \
        stm32mp157c-odyssey.dtb \
        stm32mp157c-osd32mp1-red.dtb \
        stm32mp157c-phycore-stm32mp1-3.dtb \
-       stm32mp157c-ultra-fly-sbc.dtb
+       stm32mp157c-ultra-fly-sbc.dtb \
+       stm32mp157f-dk2.dtb
 dtb-$(CONFIG_ARCH_U8500) += \
        ste-snowball.dtb \
        ste-hrefprev60-stuib.dtb \
diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi
new file mode 100644 (file)
index 0000000..89de85a
--- /dev/null
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp15-scmi.dtsi"
+
+/ {
+       reserved-memory {
+               optee@de000000 {
+                       reg = <0xde000000 0x2000000>;
+                       no-map;
+               };
+       };
+
+       arm_wdt: watchdog {
+               compatible = "arm,smc-wdt";
+               arm,smc-id = <0xbc000000>;
+               status = "disabled";
+       };
+
+};
+
+&adc {
+       vdd-supply = <&scmi_vdd>;
+       vdda-supply = <&scmi_vdd>;
+};
+
+&cpu0 {
+       clocks = <&scmi_clk CK_SCMI_MPU>;
+};
+
+&cpu1 {
+       clocks = <&scmi_clk CK_SCMI_MPU>;
+};
+
+&cryp1 {
+       clocks = <&scmi_clk CK_SCMI_CRYP1>;
+       resets = <&scmi_reset RST_SCMI_CRYP1>;
+};
+
+&cs42l51 {
+       VL-supply = <&scmi_v3v3>;
+       VD-supply = <&scmi_v1v8_audio>;
+       VA-supply = <&scmi_v1v8_audio>;
+       VAHP-supply = <&scmi_v1v8_audio>;
+};
+
+&dsi {
+       phy-dsi-supply = <&scmi_reg18>;
+       clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+};
+
+&gpioz {
+       clocks = <&scmi_clk CK_SCMI_GPIOZ>;
+};
+
+&hash1 {
+       clocks = <&scmi_clk CK_SCMI_HASH1>;
+       resets = <&scmi_reset RST_SCMI_HASH1>;
+};
+
+&i2c1 {
+       hdmi-transmitter@39 {
+               iovcc-supply = <&scmi_v3v3_hdmi>;
+               cvcc12-supply = <&scmi_v1v2_hdmi>;
+       };
+};
+
+&iwdg2 {
+       clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
+       status = "disabled";
+};
+
+&m4_rproc {
+       /delete-property/ st,syscfg-holdboot;
+       resets = <&scmi_reset RST_SCMI_MCU>,
+                <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
+       reset-names = "mcu_rst", "hold_boot";
+};
+
+&mdma1 {
+       resets = <&scmi_reset RST_SCMI_MDMA>;
+};
+
+&optee {
+       interrupt-parent = <&intc>;
+       interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+};
+
+&pwr_regulators {
+       vdd-supply = <&scmi_vdd>;
+       vdd_3v3_usbfs-supply = <&scmi_vdd_usb>;
+       status = "disabled";
+};
+
+&rcc {
+       compatible = "st,stm32mp1-rcc-secure", "syscon";
+       clock-names = "hse", "hsi", "csi", "lse", "lsi";
+       clocks = <&scmi_clk CK_SCMI_HSE>,
+                <&scmi_clk CK_SCMI_HSI>,
+                <&scmi_clk CK_SCMI_CSI>,
+                <&scmi_clk CK_SCMI_LSE>,
+                <&scmi_clk CK_SCMI_LSI>;
+};
+
+&rng1 {
+       clocks = <&scmi_clk CK_SCMI_RNG1>;
+       resets = <&scmi_reset RST_SCMI_RNG1>;
+};
+
+&rtc {
+       clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
+};
+
+&scmi_reguls {
+       scmi_vddcore: regulator@3 {
+               reg = <VOLTD_SCMI_STPMIC1_BUCK1>;
+               regulator-name = "vddcore";
+       };
+
+       scmi_vdd: regulator@5 {
+               reg = <VOLTD_SCMI_STPMIC1_BUCK3>;
+               regulator-name = "vdd";
+       };
+
+       scmi_v3v3: regulator@6 {
+               reg = <VOLTD_SCMI_STPMIC1_BUCK4>;
+               regulator-name = "v3v3";
+       };
+
+       scmi_v1v8_audio: regulator@7 {
+               reg = <VOLTD_SCMI_STPMIC1_LDO1>;
+               regulator-name = "v1v8_audio";
+       };
+
+       scmi_v3v3_hdmi: regulator@8 {
+               reg = <VOLTD_SCMI_STPMIC1_LDO2>;
+               regulator-name = "v3v3_hdmi";
+       };
+
+       scmi_vdd_usb: regulator@a {
+               reg = <VOLTD_SCMI_STPMIC1_LDO4>;
+               regulator-name = "vdd_usb";
+       };
+
+       scmi_vdda: regulator@b {
+               reg = <VOLTD_SCMI_STPMIC1_LDO5>;
+               regulator-name = "vdda";
+       };
+
+       scmi_v1v2_hdmi: regulator@c {
+               reg = <VOLTD_SCMI_STPMIC1_LDO6>;
+               regulator-name = "v1v2_hdmi";
+               regulator-min-microvolt = <1200000>;
+               regulator-max-microvolt = <1200000>;
+               regulator-always-on;
+       };
+
+       scmi_vbus_otg: regulator@f {
+               reg = <VOLTD_SCMI_STPMIC1_PWR_SW1>;
+               regulator-name = "vbus_otg";
+        };
+
+        scmi_vbus_sw: regulator@10 {
+               reg = <VOLTD_SCMI_STPMIC1_PWR_SW2>;
+               regulator-name = "vbus_sw";
+        };
+};
+
+&sdmmc1 {
+       vmmc-supply = <&scmi_v3v3>;
+};
+
+&sdmmc3 {
+       vmmc-supply = <&scmi_v3v3>;
+};
+
+&usbh_ehci {
+       hub@1 {
+               vdd-supply = <&scmi_v3v3>;
+       };
+};
+
+&usbphyc_port0 {
+       phy-supply = <&scmi_vdd_usb>;
+};
+
+&usbphyc_port1 {
+       phy-supply = <&scmi_vdd_usb>;
+};
+
+&vrefbuf {
+       vdda-supply = <&scmi_vdd>;
+};
diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts
new file mode 100644 (file)
index 0000000..43375c4
--- /dev/null
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xf.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include "stm32mp15xx-dkx.dtsi"
+#include "stm32mp157f-dk2-scmi.dtsi"
+
+/ {
+       model = "STMicroelectronics STM32MP157F-DK2 Discovery Board";
+       compatible = "st,stm32mp157f-dk2", "st,stm32mp157";
+
+       aliases {
+               ethernet0 = &ethernet0;
+               serial3 = &usart2;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       wifi_pwrseq: wifi-pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
+       };
+};
+
+&arm_wdt {
+       timeout-sec = <32>;
+       status = "okay";
+};
+
+&cryp1 {
+       status = "okay";
+};
+
+&dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+
+       panel@0 {
+               compatible = "orisetech,otm8009a";
+               reg = <0>;
+               reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+               power-supply = <&scmi_v3v3>;
+               status = "okay";
+
+               port {
+                       panel_in: endpoint {
+                               remote-endpoint = <&dsi_out>;
+                       };
+               };
+       };
+};
+
+&dsi_in {
+       remote-endpoint = <&ltdc_ep1_out>;
+};
+
+&dsi_out {
+       remote-endpoint = <&panel_in>;
+};
+
+&i2c1 {
+       touchscreen@38 {
+               compatible = "focaltech,ft6236";
+               reg = <0x38>;
+               interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+               interrupt-parent = <&gpiof>;
+               touchscreen-size-x = <480>;
+               touchscreen-size-y = <800>;
+               status = "okay";
+       };
+};
+
+/* I2C4 is managed by OP-TEE */
+&i2c4 {
+       status = "disabled";
+
+       /* i2c4 subnodes, which won't be managed by Linux */
+       typec@28 {
+               status = "disabled";
+               connector {
+                       status = "disabled";
+               };
+       };
+
+       stpmic@33 {
+               status = "disabled";
+       };
+};
+
+&ltdc {
+       status = "okay";
+
+       port {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ltdc_ep1_out: endpoint@1 {
+                       reg = <1>;
+                       remote-endpoint = <&dsi_in>;
+               };
+       };
+};
+
+&rtc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&rtc_rsvd_pins_a>;
+
+       rtc_lsco_pins_a: rtc-lsco-0 {
+               pins = "out2_rmp";
+               function = "lsco";
+       };
+};
+
+/* Wifi */
+&sdmmc2 {
+       pinctrl-names = "default", "opendrain", "sleep";
+       pinctrl-0 = <&sdmmc2_b4_pins_a>;
+       pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
+       pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
+       non-removable;
+       cap-sdio-irq;
+       st,neg-edge;
+       bus-width = <4>;
+       vmmc-supply = <&scmi_v3v3>;
+       mmc-pwrseq = <&wifi_pwrseq>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+
+       brcmf: wifi@1 {
+               reg = <1>;
+               compatible = "brcm,bcm4329-fmac";
+               pinctrl-names = "default";
+               pinctrl-0 = <&rtc_lsco_pins_a>;
+       };
+};
+
+/* Bluetooth */
+&usart2 {
+       pinctrl-names = "default", "sleep", "idle";
+       pinctrl-0 = <&usart2_pins_c>;
+       pinctrl-1 = <&usart2_sleep_pins_c>;
+       pinctrl-2 = <&usart2_idle_pins_c>;
+       uart-has-rtscts;
+       status = "okay";
+
+       bluetooth {
+               shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
+               compatible = "brcm,bcm43438-bt";
+               max-speed = <3000000>;
+               vbat-supply = <&scmi_v3v3>;
+               vddio-supply = <&scmi_v3v3>;
+       };
+};
+
+/* Since I2C4 is disabled, STUSB1600 is also disabled so there is no Type-C support */
+&usbotg_hs {
+       dr_mode = "peripheral";
+       role-switch-default-mode = "peripheral";
+       /*
+        * Forcing dr_mode = "peripheral"/"role-switch-default-mode = "peripheral";
+        * will cause the pull-up on D+/D- to be raised as soon as the OTG is configured at runtime,
+        * regardless of the presence of VBUS. Notice that on self-powered devices like
+        * stm32mp157f-dk2, this isn't compliant with the USB standard. That's why usbotg_hs is kept
+        * disabled here.
+        */
+       status = "disabled";
+};