]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: rockchip: Enable OTP controller for RK356x
authorHeiko Stuebner <heiko@sntech.de>
Thu, 12 Mar 2026 21:30:18 +0000 (22:30 +0100)
committerHeiko Stuebner <heiko@sntech.de>
Tue, 24 Mar 2026 22:23:21 +0000 (23:23 +0100)
Enable the One Time Programmable Controller (OTPC) in RK356x and add
an initial nvmem fixed layout.

Tested-by: Diederik de Haas <diederik@cknow-tech.com> # NanoPi R5S, PineNote
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patch.msgid.link/20260312213019.13965-3-heiko@sntech.de
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi

index 68b48606f6010c95f89eadfe7814ec5b386e6156..c8321af7de7dd97e5faa2cc3603988b84bfdd99a 100644 (file)
                status = "disabled";
        };
 
+       otp: efuse@fe38c000 {
+               compatible = "rockchip,rk3568-otp";
+               reg = <0x0 0xfe38c000 0x0 0x4000>;
+               clocks = <&cru CLK_OTPC_NS_USR>, <&cru PCLK_OTPC_NS>,
+                        <&cru PCLK_OTPPHY>, <&cru CLK_OTPC_NS_SBPI>;
+               clock-names = "otp", "apb_pclk", "phy", "sbpi";
+               resets = <&cru SRST_OTPC_NS_USR>, <&cru SRST_P_OTPC_NS>,
+                        <&cru SRST_OTPPHY>, <&cru SRST_OTPC_NS_SBPI>;
+               reset-names = "otp", "apb", "phy", "sbpi";
+
+               nvmem-layout {
+                       compatible = "fixed-layout";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       cpu_code: cpu-code@2 {
+                               reg = <0x02 0x2>;
+                       };
+
+                       otp_cpu_version: cpu-version@8 {
+                               reg = <0x08 0x1>;
+                               bits = <3 3>;
+                       };
+
+                       otp_id: id@a {
+                               reg = <0x0a 0x10>;
+                       };
+
+                       cpu_leakage: cpu-leakage@1a {
+                               reg = <0x1a 0x1>;
+                       };
+
+                       log_leakage: log-leakage@1b {
+                               reg = <0x1b 0x1>;
+                       };
+
+                       npu_leakage: npu-leakage@1c {
+                               reg = <0x1c 0x1>;
+                       };
+
+                       gpu_leakage: gpu-leakage@1d {
+                               reg = <0x1d 0x1>;
+                       };
+               };
+       };
+
        i2s0_8ch: i2s@fe400000 {
                compatible = "rockchip,rk3568-i2s-tdm";
                reg = <0x0 0xfe400000 0x0 0x1000>;