extern s32 patch__flush_hash_A0, patch__flush_hash_A1, patch__flush_hash_A2;
extern s32 patch__flush_hash_B;
+#include <linux/sizes.h>
+#include <linux/align.h>
+
#include <asm/reg.h>
#include <asm/task_size_32.h>
static __always_inline void update_user_segment(u32 n, u32 val)
{
- if (n << 28 < TASK_SIZE)
+ if (n << 28 < ALIGN(TASK_SIZE, SZ_256M))
mtsr(val + n * 0x111, n << 28);
}
#ifndef CONFIG_PPC64
DEFINE(TASK_SIZE, TASK_SIZE);
- DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
+ DEFINE(NUM_USER_SEGMENTS, ALIGN(TASK_SIZE, SZ_256M) >> 28);
#endif /* ! CONFIG_PPC64 */
/* datapage offsets for use by vdso */
lwz r2,0(r2) /* get pmd entry */
#ifdef CONFIG_EXECMEM
rlwinm r3, r0, 4, 0xf
- subi r3, r3, (TASK_SIZE >> 28) & 0xf
+ subi r3, r3, NUM_USER_SEGMENTS
#endif
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
beq- InstructionAddressInvalid /* return if no mapping */
lwz r2,0(r1) /* get pmd entry */
rlwinm r3, r0, 4, 0xf
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
- subi r3, r3, (TASK_SIZE >> 28) & 0xf
+ subi r3, r3, NUM_USER_SEGMENTS
beq- 2f /* bail if no mapping */
1: rlwimi r2,r0,22,20,29 /* insert next 10 bits of address */
lwz r2,0(r2) /* get linux-style pte */
lwz r2,0(r1) /* get pmd entry */
rlwinm r3, r0, 4, 0xf
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
- subi r3, r3, (TASK_SIZE >> 28) & 0xf
+ subi r3, r3, NUM_USER_SEGMENTS
beq- 2f /* bail if no mapping */
1:
rlwimi r2,r0,22,20,29 /* insert next 10 bits of address */
BUILD_BUG_ON(ALIGN_DOWN(MODULES_VADDR, SZ_256M) < TASK_SIZE);
- for (i = TASK_SIZE >> 28; i < 16; i++) {
+ for (i = ALIGN(TASK_SIZE, SZ_256M) >> 28; i < 16; i++) {
/* Do not set NX on VM space for modules */
if (is_module_segment(i << 28))
continue;